| Loop Id: 2228 | Module: exec | Source: ams.c:608-609 | Coverage: 0.26% |
|---|
| Loop Id: 2228 | Module: exec | Source: ams.c:608-609 | Coverage: 0.26% |
|---|
0x536d74 VMOVSD (%RAX),%XMM2 [3] |
0x536d78 ADD $0x40,%RAX |
0x536d7c VANDPD %XMM15,%XMM2,%XMM6 |
0x536d81 VADDSD %XMM6,%XMM0,%XMM7 |
0x536d85 VMOVSD %XMM7,(%RDX) [2] |
0x536d89 VMOVSD -0x38(%RAX),%XMM9 [1] |
0x536d8e VANDPD %XMM15,%XMM9,%XMM1 |
0x536d93 VADDSD %XMM1,%XMM7,%XMM3 |
0x536d97 VMOVSD %XMM3,(%RDX) [2] |
0x536d9b VMOVSD -0x30(%RAX),%XMM4 [1] |
0x536da0 VANDPD %XMM15,%XMM4,%XMM5 |
0x536da5 VADDSD %XMM5,%XMM3,%XMM8 |
0x536da9 VMOVSD %XMM8,(%RDX) [2] |
0x536dad VMOVSD -0x28(%RAX),%XMM11 [1] |
0x536db2 VANDPD %XMM15,%XMM11,%XMM12 |
0x536db7 VADDSD %XMM12,%XMM8,%XMM13 |
0x536dbc VMOVSD %XMM13,(%RDX) [2] |
0x536dc0 VMOVSD -0x20(%RAX),%XMM0 [1] |
0x536dc5 VANDPD %XMM15,%XMM0,%XMM2 |
0x536dca VADDSD %XMM2,%XMM13,%XMM6 |
0x536dce VMOVSD %XMM6,(%RDX) [2] |
0x536dd2 VMOVSD -0x18(%RAX),%XMM7 [1] |
0x536dd7 VANDPD %XMM15,%XMM7,%XMM9 |
0x536ddc VADDSD %XMM9,%XMM6,%XMM3 |
0x536de1 VMOVSD %XMM3,(%RDX) [2] |
0x536de5 VMOVSD -0x10(%RAX),%XMM1 [1] |
0x536dea VANDPD %XMM15,%XMM1,%XMM4 |
0x536def VADDSD %XMM4,%XMM3,%XMM5 |
0x536df3 VMOVSD %XMM5,(%RDX) [2] |
0x536df7 VMOVSD -0x8(%RAX),%XMM8 [1] |
0x536dfc VANDPD %XMM15,%XMM8,%XMM11 |
0x536e01 VADDSD %XMM11,%XMM5,%XMM0 |
0x536e06 VMOVSD %XMM0,(%RDX) [2] |
0x536e0a CMP %RSI,%RAX |
0x536e0d JNE 536d74 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 608 - 609 |
-------------------------------------------------------------------------------- |
608: for (j = A_diag_I[i]; j < A_diag_I[i+1]; j++) |
609: l1_norm[i] += fabs(A_diag_data[j]); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►94.74+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 | |
| ►5.26+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.90 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.76 |
| Bottlenecks | |
| Function | hypre_ParCSRComputeL1Norms |
| Source | ams.c:608-609 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 16.80 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 8.50 |
| DIV/SQRT cycles | 5.33 |
| P0 cycles | 5.33 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 5.33 |
| P5 cycles | 2.00 |
| P6 cycles | 5.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | 32.14 |
| Stall cycles (UFS) | 23.14 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.25 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 25.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 15.63 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.90 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 3.76 |
| Bottlenecks | |
| Function | hypre_ParCSRComputeL1Norms |
| Source | ams.c:608-609 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 16.80 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 8.50 |
| DIV/SQRT cycles | 5.33 |
| P0 cycles | 5.33 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 5.33 |
| P5 cycles | 2.00 |
| P6 cycles | 5.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 32 |
| FE+BE cycles (UFS) | 32.14 |
| Stall cycles (UFS) | 23.14 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.25 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 25.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 15.63 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Path / |
| Function | hypre_ParCSRComputeL1Norms |
| Source file and lines | ams.c:608-609 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 159 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 14 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 8.50 cycles |
| front end | 8.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 5.33 | 5.33 | 5.33 | 5.33 | 8.00 | 5.33 | 2.00 | 5.33 |
| cycles | 5.33 | 5.33 | 5.33 | 5.33 | 8.00 | 5.33 | 2.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| FE+BE cycles | 32.14 |
| Stall cycles | 23.14 |
| RS full (events) | 31.54 |
| Front-end | 8.50 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 25% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RAX),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VANDPD %XMM15,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM6,%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x38(%RAX),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM9,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM1,%XMM7,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x30(%RAX),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM4,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM5,%XMM3,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM8,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x28(%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM11,%XMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM12,%XMM8,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x20(%RAX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM0,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM2,%XMM13,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM6,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x18(%RAX),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM7,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM9,%XMM6,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x10(%RAX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM1,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM4,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM5,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x8(%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM8,%XMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM11,%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM0,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 536d74 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_ParCSRComputeL1Norms |
| Source file and lines | ams.c:608-609 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 159 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 14 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 8.50 cycles |
| front end | 8.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 5.33 | 5.33 | 5.33 | 5.33 | 8.00 | 5.33 | 2.00 | 5.33 |
| cycles | 5.33 | 5.33 | 5.33 | 5.33 | 8.00 | 5.33 | 2.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 32.00 |
| FE+BE cycles | 32.14 |
| Stall cycles | 23.14 |
| RS full (events) | 31.54 |
| Front-end | 8.50 |
| Dispatch | 8.00 |
| Data deps. | 32.00 |
| Overall L1 | 32.00 |
| all | 25% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RAX),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD $0x40,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VANDPD %XMM15,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM6,%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x38(%RAX),%XMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM9,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM1,%XMM7,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x30(%RAX),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM4,%XMM5 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM5,%XMM3,%XMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM8,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x28(%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM11,%XMM12 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM12,%XMM8,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x20(%RAX),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM0,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM2,%XMM13,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM6,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x18(%RAX),%XMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM7,%XMM9 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM9,%XMM6,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM3,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x10(%RAX),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM1,%XMM4 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM4,%XMM3,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM5,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD -0x8(%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM15,%XMM8,%XMM11 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VADDSD %XMM11,%XMM5,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM0,(%RDX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RSI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 536d74 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
