| Loop Id: 2690 | Module: exec | Source: ams.c:720-722 | Coverage: 0.08% |
|---|
| Loop Id: 2690 | Module: exec | Source: ams.c:720-722 | Coverage: 0.08% |
|---|
0x4a8260 ADD $0x20,%RCX |
0x4a8264 DEC %RAX |
0x4a8267 JE 4a813e |
0x4a826d MOV -0x18(%R8,%RCX,1),%RDX [4] |
0x4a8272 VUCOMISD (%RDI,%RDX,8),%XMM0 [1] |
0x4a8277 JA 4a82a0 |
0x4a8279 MOV -0x10(%R8,%RCX,1),%RDX [4] |
0x4a827e VUCOMISD (%RDI,%RDX,8),%XMM0 [6] |
0x4a8283 JA 4a82bc |
0x4a8285 MOV -0x8(%R8,%RCX,1),%RDX [4] |
0x4a828a VUCOMISD (%RDI,%RDX,8),%XMM0 [5] |
0x4a828f JA 4a82d8 |
0x4a8291 MOV (%R8,%RCX,1),%RDX [4] |
0x4a8295 VUCOMISD (%RDI,%RDX,8),%XMM0 [3] |
0x4a829a JBE 4a8260 |
0x4a829c JMP 4a82f7 |
0x4a82a0 VMOVSD -0x18(%RBX,%RCX,1),%XMM2 [2] |
0x4a82a6 VXORPD %XMM1,%XMM2,%XMM2 |
0x4a82aa VMOVLPD %XMM2,-0x18(%RBX,%RCX,1) [2] |
0x4a82b0 MOV -0x10(%R8,%RCX,1),%RDX [4] |
0x4a82b5 VUCOMISD (%RDI,%RDX,8),%XMM0 [6] |
0x4a82ba JBE 4a8285 |
0x4a82bc VMOVSD -0x10(%RBX,%RCX,1),%XMM2 [2] |
0x4a82c2 VXORPD %XMM1,%XMM2,%XMM2 |
0x4a82c6 VMOVLPD %XMM2,-0x10(%RBX,%RCX,1) [2] |
0x4a82cc MOV -0x8(%R8,%RCX,1),%RDX [4] |
0x4a82d1 VUCOMISD (%RDI,%RDX,8),%XMM0 [5] |
0x4a82d6 JBE 4a8291 |
0x4a82d8 VMOVSD -0x8(%RBX,%RCX,1),%XMM2 [2] |
0x4a82de VXORPD %XMM1,%XMM2,%XMM2 |
0x4a82e2 VMOVLPD %XMM2,-0x8(%RBX,%RCX,1) [2] |
0x4a82e8 MOV (%R8,%RCX,1),%RDX [4] |
0x4a82ec VUCOMISD (%RDI,%RDX,8),%XMM0 [3] |
0x4a82f1 JBE 4a8260 |
0x4a82f7 VMOVSD (%RBX,%RCX,1),%XMM2 [2] |
0x4a82fc VXORPD %XMM1,%XMM2,%XMM2 |
0x4a8300 VMOVLPD %XMM2,(%RBX,%RCX,1) [2] |
0x4a8305 JMP 4a8260 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/ams.c: 720 - 722 |
-------------------------------------------------------------------------------- |
720: for (i = 0; i < num_rows; i++) |
721: if (A_diag_data[A_diag_I[i]] < 0) |
722: l1_norm[i] = -l1_norm[i]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_BoomerAMGSetup | par_amg_setup.c:1381 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.29 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.25 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_ParCSRComputeL1Norms |
| Source | ams.c:720-722 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 11.25 |
| CQA cycles if no scalar integer | 8.75 |
| CQA cycles if FP arith vectorized | 11.25 |
| CQA cycles if fully vectorized | 1.41 |
| Front-end cycles | 11.25 |
| DIV/SQRT cycles | 8.50 |
| P0 cycles | 3.00 |
| P1 cycles | 9.00 |
| P2 cycles | 9.00 |
| P3 cycles | 4.00 |
| P4 cycles | 3.00 |
| P5 cycles | 8.50 |
| P6 cycles | 4.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 11.44 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 38.00 |
| Nb uops | 45.00 |
| Nb loads | 18.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.64 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 144.00 |
| Bytes stored | 32.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 21.05 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 36.36 |
| Vector-efficiency ratio all | 15.13 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 17.05 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.29 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.25 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_ParCSRComputeL1Norms |
| Source | ams.c:720-722 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 11.25 |
| CQA cycles if no scalar integer | 8.75 |
| CQA cycles if FP arith vectorized | 11.25 |
| CQA cycles if fully vectorized | 1.41 |
| Front-end cycles | 11.25 |
| DIV/SQRT cycles | 8.50 |
| P0 cycles | 3.00 |
| P1 cycles | 9.00 |
| P2 cycles | 9.00 |
| P3 cycles | 4.00 |
| P4 cycles | 3.00 |
| P5 cycles | 8.50 |
| P6 cycles | 4.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 11.44 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 38.00 |
| Nb uops | 45.00 |
| Nb loads | 18.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.64 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 144.00 |
| Bytes stored | 32.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 21.05 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 36.36 |
| Vector-efficiency ratio all | 15.13 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 17.05 |
| Path / |
| Function | hypre_ParCSRComputeL1Norms |
| Source file and lines | ams.c:720-722 |
| Module | exec |
| nb instructions | 38 |
| nb uops | 45 |
| loop length | 168 |
| used x86 registers | 6 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 11.25 cycles |
| front end | 11.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 3.00 | 9.00 | 9.00 | 4.00 | 3.00 | 8.50 | 4.00 |
| cycles | 8.50 | 3.00 | 9.00 | 9.00 | 4.00 | 3.00 | 8.50 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 11.44 |
| Stall cycles | 0.00 |
| Front-end | 11.25 |
| Dispatch | 9.00 |
| Overall L1 | 11.25 |
| all | 21% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 36% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD $0x20,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4a813e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x18(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x10(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82bc | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x8(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 4a82f7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| VMOVSD -0x18(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x18(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x10(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8285 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD -0x10(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x10(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x8(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8291 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD -0x8(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x8(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV (%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| JMP 4a8260 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_ParCSRComputeL1Norms |
| Source file and lines | ams.c:720-722 |
| Module | exec |
| nb instructions | 38 |
| nb uops | 45 |
| loop length | 168 |
| used x86 registers | 6 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 11.25 cycles |
| front end | 11.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 3.00 | 9.00 | 9.00 | 4.00 | 3.00 | 8.50 | 4.00 |
| cycles | 8.50 | 3.00 | 9.00 | 9.00 | 4.00 | 3.00 | 8.50 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 11.44 |
| Stall cycles | 0.00 |
| Front-end | 11.25 |
| Dispatch | 9.00 |
| Overall L1 | 11.25 |
| all | 21% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 36% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD $0x20,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4a813e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x18(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x10(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82bc | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x8(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JA 4a82d8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 4a82f7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| VMOVSD -0x18(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x18(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x10(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8285 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD -0x10(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x10(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x8(%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8291 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD -0x8(%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,-0x8(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV (%R8,%RCX,1),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUCOMISD (%RDI,%RDX,8),%XMM0 | 2 | 1 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4a8260 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%RCX,1),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM1,%XMM2,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVLPD %XMM2,(%RBX,%RCX,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| JMP 4a8260 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
