| Loop Id: 318 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
|---|
| Loop Id: 318 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
|---|
0x4436a5 CALL 5b50f0 <hypre_Rand> |
0x4436aa LEA 0x1(%RBX),%R13 |
0x4436ae VADDSD (%R12,%RBX,8),%XMM0,%XMM7 [1] |
0x4436b4 VMOVSD %XMM7,(%R12,%RBX,8) [1] |
0x4436ba CALL 5b50f0 <hypre_Rand> |
0x4436bf VADDSD (%R12,%R13,8),%XMM0,%XMM8 [2] |
0x4436c5 VMOVSD %XMM8,(%R12,%R13,8) [2] |
0x4436cb LEA 0x2(%RBX),%R13 |
0x4436cf CALL 5b50f0 <hypre_Rand> |
0x4436d4 VADDSD (%R12,%R13,8),%XMM0,%XMM9 [2] |
0x4436da VMOVSD %XMM9,(%R12,%R13,8) [2] |
0x4436e0 LEA 0x3(%RBX),%R13 |
0x4436e4 CALL 5b50f0 <hypre_Rand> |
0x4436e9 VADDSD (%R12,%R13,8),%XMM0,%XMM10 [2] |
0x4436ef VMOVSD %XMM10,(%R12,%R13,8) [2] |
0x4436f5 LEA 0x4(%RBX),%R13 |
0x4436f9 CALL 5b50f0 <hypre_Rand> |
0x4436fe VADDSD (%R12,%R13,8),%XMM0,%XMM11 [2] |
0x443704 VMOVSD %XMM11,(%R12,%R13,8) [2] |
0x44370a LEA 0x5(%RBX),%R13 |
0x44370e CALL 5b50f0 <hypre_Rand> |
0x443713 VADDSD (%R12,%R13,8),%XMM0,%XMM12 [2] |
0x443719 VMOVSD %XMM12,(%R12,%R13,8) [2] |
0x44371f LEA 0x6(%RBX),%R13 |
0x443723 CALL 5b50f0 <hypre_Rand> |
0x443728 VADDSD (%R12,%R13,8),%XMM0,%XMM13 [2] |
0x44372e VMOVSD %XMM13,(%R12,%R13,8) [2] |
0x443734 LEA 0x7(%RBX),%R13 |
0x443738 ADD $0x8,%RBX |
0x44373c CALL 5b50f0 <hypre_Rand> |
0x443741 VADDSD (%R12,%R13,8),%XMM0,%XMM14 [2] |
0x443747 VMOVSD %XMM14,(%R12,%R13,8) [2] |
0x44374d CMP %RBX,%R14 |
0x443750 JNE 4436a5 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_indepset.c: 65 - 67 |
-------------------------------------------------------------------------------- |
65: for (i = 0; i < S_num_nodes; i++) |
66: { |
67: measure_array[i] += hypre_Rand(); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2186 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:612 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.00 |
| CQA speedup if FP arith vectorized | 1.78 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.31 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGIndepSetInit |
| Source | par_indepset.c:65-67 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 9.00 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 12.25 |
| DIV/SQRT cycles | 6.50 |
| P0 cycles | 5.25 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 16.00 |
| P4 cycles | 5.25 |
| P5 cycles | 8.00 |
| P6 cycles | 8.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 10.41 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 34.00 |
| Nb uops | 41.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.00 |
| CQA speedup if FP arith vectorized | 1.78 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.31 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGIndepSetInit |
| Source | par_indepset.c:65-67 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 9.00 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 12.25 |
| DIV/SQRT cycles | 6.50 |
| P0 cycles | 5.25 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 16.00 |
| P4 cycles | 5.25 |
| P5 cycles | 8.00 |
| P6 cycles | 8.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 10.41 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 34.00 |
| Nb uops | 41.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | hypre_BoomerAMGIndepSetInit |
| Source file and lines | par_indepset.c:65-67 |
| Module | exec |
| nb instructions | 34 |
| nb uops | 41 |
| loop length | 177 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 12.25 cycles |
| front end | 12.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 6.50 | 5.25 | 8.00 | 8.00 | 16.00 | 5.25 | 8.00 | 8.00 |
| cycles | 6.50 | 5.25 | 8.00 | 8.00 | 16.00 | 5.25 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 10.41 |
| Stall cycles | 0.00 |
| Front-end | 12.25 |
| Dispatch | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| LEA 0x1(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R12,%RBX,8),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%R12,%RBX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM8,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x2(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM9,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x3(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x4(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM11,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x5(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM12,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x6(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x7(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD $0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM14,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RBX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4436a5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_BoomerAMGIndepSetInit |
| Source file and lines | par_indepset.c:65-67 |
| Module | exec |
| nb instructions | 34 |
| nb uops | 41 |
| loop length | 177 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 9 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 12.25 cycles |
| front end | 12.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 6.50 | 5.25 | 8.00 | 8.00 | 16.00 | 5.25 | 8.00 | 8.00 |
| cycles | 6.50 | 5.25 | 8.00 | 8.00 | 16.00 | 5.25 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 10.41 |
| Stall cycles | 0.00 |
| Front-end | 12.25 |
| Dispatch | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| LEA 0x1(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R12,%RBX,8),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%R12,%RBX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM8,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x2(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM9,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x3(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x4(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM11,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x5(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM12,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x6(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| LEA 0x7(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD $0x8,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CALL 5b50f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VADDSD (%R12,%R13,8),%XMM0,%XMM14 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM14,(%R12,%R13,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RBX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4436a5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
