| Loop Id: 3858 | Module: exec | Source: csr_matop.c:286-298 | Coverage: 0.65% |
|---|
| Loop Id: 3858 | Module: exec | Source: csr_matop.c:286-298 | Coverage: 0.65% |
|---|
0x4e57a0 VADDSD (%RDX,%RSI,8),%XMM1,%XMM1 [5] |
0x4e57a5 VMOVSD %XMM1,(%RDX,%RSI,8) [5] |
0x4e57aa INC %RDI |
0x4e57ad CMP %RBX,%RDI |
0x4e57b0 JGE 4e5760 |
0x4e57b2 MOV (%R15,%RDI,8),%RCX [6] |
0x4e57b6 MOV (%R13,%RCX,8),%RSI [2] |
0x4e57bb VMULSD (%R12,%RDI,8),%XMM0,%XMM1 [3] |
0x4e57c1 CMP %R9,%RSI |
0x4e57c4 JGE 4e57a0 |
0x4e57c6 MOV %RAX,(%R13,%RCX,8) [2] |
0x4e57cb MOV -0x80(%RBP),%RSI [7] |
0x4e57cf MOV (%RSI),%RSI [1] |
0x4e57d2 MOV %RCX,(%RSI,%RAX,8) [8] |
0x4e57d6 MOV (%R13,%RCX,8),%RCX [2] |
0x4e57db VMOVSD %XMM1,(%RDX,%RCX,8) [5] |
0x4e57e0 INC %RAX |
0x4e57e3 MOV 0x8(%R14,%R10,8),%RBX [4] |
0x4e57e8 INC %RDI |
0x4e57eb CMP %RBX,%RDI |
0x4e57ee JL 4e57b2 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matop.c: 286 - 298 |
-------------------------------------------------------------------------------- |
286: for (ib = B_i[ja]; ib < B_i[ja+1]; ib++) |
287: { |
288: jb = B_j[ib]; |
289: b_entry = B_data[ib]; |
290: if (B_marker[jb] < row_start) |
291: { |
292: B_marker[jb] = counter; |
293: C_j[B_marker[jb]] = jb; |
294: C_data[B_marker[jb]] = a_entry*b_entry; |
295: counter++; |
296: } |
297: else |
298: C_data[B_marker[jb]] += a_entry*b_entry; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_CSRMatrixMultiply | csr_matop.c:185 | exec |
| ○ | hypre_ParTMatmul | par_csr_matop.c:3285 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:1227 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.80 |
| CQA speedup if FP arith vectorized | 1.64 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source | csr_matop.c:286-298 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.38 |
| CQA cycles if no scalar integer | 1.88 |
| CQA cycles if FP arith vectorized | 2.06 |
| CQA cycles if fully vectorized | 0.42 |
| Front-end cycles | 3.38 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 2.75 |
| P2 cycles | 2.75 |
| P3 cycles | 2.00 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 2.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.61 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 13.00 |
| Nb uops | 12.00 |
| Nb loads | 5.50 |
| Nb stores | 2.00 |
| Nb stack references | 0.50 |
| FLOP/cycle | 0.44 |
| Nb FLOP add-sub | 0.50 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.27 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 44.00 |
| Bytes stored | 16.00 |
| Stride 0 | 1.00 |
| Stride 1 | 2.50 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.50 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.29 |
| CQA speedup if FP arith vectorized | 1.33 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.14 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source | csr_matop.c:286-298 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.00 |
| CQA cycles if no scalar integer | 1.75 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 0.50 |
| Front-end cycles | 4.00 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 3.50 |
| P2 cycles | 3.50 |
| P3 cycles | 3.00 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 3.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 4.22 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 16.00 |
| Nb uops | 15.00 |
| Nb loads | 7.00 |
| Nb stores | 3.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 0.25 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 24.00 |
| Stride 0 | 2.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.38 |
| CQA speedup if FP arith vectorized | 2.44 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.38 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source | csr_matop.c:286-298 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.75 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 1.13 |
| CQA cycles if fully vectorized | 0.34 |
| Front-end cycles | 2.75 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.50 |
| P5 cycles | 1.50 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.00 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 10.00 |
| Nb uops | 9.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.73 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.55 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 32.00 |
| Bytes stored | 8.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source file and lines | csr_matop.c:286-298 |
| Module | exec |
| nb instructions | 13 |
| nb uops | 12 |
| loop length | 50 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0.50 |
| micro-operation queue | 3.38 cycles |
| front end | 3.38 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 2.75 | 2.75 | 2.00 | 1.50 | 1.50 | 2.00 |
| cycles | 1.50 | 1.50 | 2.75 | 2.75 | 2.00 | 1.50 | 1.50 | 2.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.61 |
| Stall cycles | 0.00 |
| Front-end | 3.38 |
| Dispatch | 2.75 |
| Data deps. | 1.00 |
| Overall L1 | 3.38 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source file and lines | csr_matop.c:286-298 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 15 |
| loop length | 62 |
| used x86 registers | 13 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 3.50 | 3.50 | 3.00 | 1.50 | 1.50 | 3.00 |
| cycles | 1.50 | 1.50 | 3.50 | 3.50 | 3.00 | 1.50 | 1.50 | 3.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 4.22 |
| Stall cycles | 0.00 |
| Front-end | 4.00 |
| Dispatch | 3.50 |
| Data deps. | 1.00 |
| Overall L1 | 4.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV (%R15,%RDI,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RCX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDI,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 4e57a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %RAX,(%R13,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x80(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RSI),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RCX,(%RSI,%RAX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV (%R13,%RCX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM1,(%RDX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV 0x8(%R14,%R10,8),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RBX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JL 4e57b2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_CSRMatrixMultiply.extracted |
| Source file and lines | csr_matop.c:286-298 |
| Module | exec |
| nb instructions | 10 |
| nb uops | 9 |
| loop length | 38 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 2.75 cycles |
| front end | 2.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 2.00 | 2.00 | 1.00 | 1.50 | 1.50 | 1.00 |
| cycles | 1.50 | 1.50 | 2.00 | 2.00 | 1.00 | 1.50 | 1.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.00 |
| Stall cycles | 0.00 |
| Front-end | 2.75 |
| Dispatch | 2.00 |
| Data deps. | 1.00 |
| Overall L1 | 2.75 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VADDSD (%RDX,%RSI,8),%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RDX,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RBX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 4e5760 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%R15,%RDI,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RCX,8),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDI,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %R9,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 4e57a0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
