| Loop Id: 3627 | Module: exec | Source: IJMatrix_parcsr.c:207-208 | Coverage: 0.01% |
|---|
| Loop Id: 3627 | Module: exec | Source: IJMatrix_parcsr.c:207-208 | Coverage: 0.01% |
|---|
0x4d8060 ADD -0x38(%R12,%RSI,1),%RDX [1] |
0x4d8065 MOV %RDX,-0x30(%RAX,%RSI,1) [2] |
0x4d806a ADD -0x30(%R12,%RSI,1),%RDX [1] |
0x4d806f MOV %RDX,-0x28(%RAX,%RSI,1) [2] |
0x4d8074 ADD -0x28(%R12,%RSI,1),%RDX [1] |
0x4d8079 MOV %RDX,-0x20(%RAX,%RSI,1) [2] |
0x4d807e ADD -0x20(%R12,%RSI,1),%RDX [1] |
0x4d8083 MOV %RDX,-0x18(%RAX,%RSI,1) [2] |
0x4d8088 ADD -0x18(%R12,%RSI,1),%RDX [1] |
0x4d808d MOV %RDX,-0x10(%RAX,%RSI,1) [2] |
0x4d8092 ADD -0x10(%R12,%RSI,1),%RDX [1] |
0x4d8097 MOV %RDX,-0x8(%RAX,%RSI,1) [2] |
0x4d809c ADD -0x8(%R12,%RSI,1),%RDX [1] |
0x4d80a1 MOV %RDX,(%RAX,%RSI,1) [2] |
0x4d80a5 ADD (%R12,%RSI,1),%RDX [1] |
0x4d80a9 MOV %RDX,0x8(%RAX,%RSI,1) [2] |
0x4d80ae ADD $0x40,%RSI |
0x4d80b2 DEC %RCX |
0x4d80b5 JNE 4d8060 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/IJ_mv/IJMatrix_parcsr.c: 207 - 208 |
-------------------------------------------------------------------------------- |
207: for (i = 0; i < local_num_rows; i++) |
208: offd_i[i+1] = offd_i[i] + offdiag_sizes[i]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | HYPRE_IJMatrixSetDiagOffdSizes | HYPRE_IJMatrix.c:770 | exec |
| ○ | BuildIJLaplacian27pt.extracted | amg.c:1385 | exec |
| ○ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | BuildIJLaplacian27pt | amg.c:760 | exec |
| ○ | main | amg.c:274 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P4, |
| Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
| Source | IJMatrix_parcsr.c:207-208 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 6.50 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 2.50 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 5.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 8.11 |
| Stall cycles (UFS) | 1.22 |
| Nb insns | 19.00 |
| Nb uops | 18.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P4, |
| Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
| Source | IJMatrix_parcsr.c:207-208 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 6.50 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 2.50 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 5.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 8.11 |
| Stall cycles (UFS) | 1.22 |
| Nb insns | 19.00 |
| Nb uops | 18.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 16.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
| Source file and lines | IJMatrix_parcsr.c:207-208 |
| Module | exec |
| nb instructions | 19 |
| nb uops | 18 |
| loop length | 87 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 5.33 | 5.33 | 8.00 | 2.50 | 2.50 | 5.33 |
| cycles | 2.50 | 2.50 | 5.33 | 5.33 | 8.00 | 2.50 | 2.50 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 8.11 |
| Stall cycles | 1.22 |
| RS full (events) | 4.36 |
| Front-end | 6.50 |
| Dispatch | 8.00 |
| Data deps. | 8.00 |
| Overall L1 | 8.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD -0x38(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x30(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x30(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x28(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x28(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x20(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x20(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x18(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x18(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x10(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x10(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x8(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD (%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x40,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4d8060 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_IJMatrixSetDiagOffdSizesParCSR |
| Source file and lines | IJMatrix_parcsr.c:207-208 |
| Module | exec |
| nb instructions | 19 |
| nb uops | 18 |
| loop length | 87 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 5.33 | 5.33 | 8.00 | 2.50 | 2.50 | 5.33 |
| cycles | 2.50 | 2.50 | 5.33 | 5.33 | 8.00 | 2.50 | 2.50 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 8.11 |
| Stall cycles | 1.22 |
| RS full (events) | 4.36 |
| Front-end | 6.50 |
| Dispatch | 8.00 |
| Data deps. | 8.00 |
| Overall L1 | 8.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD -0x38(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x30(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x30(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x28(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x28(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x20(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x20(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x18(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x18(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x10(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x10(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,-0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD -0x8(%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD (%R12,%RSI,1),%RDX | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RDX,0x8(%RAX,%RSI,1) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x40,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4d8060 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
