| Loop Id: 3121 | Module: exec | Source: csr_matvec.c:310-312 | Coverage: 0.22% |
|---|
| Loop Id: 3121 | Module: exec | Source: csr_matvec.c:310-312 | Coverage: 0.22% |
|---|
0x5a1c9b VMOVDQU64 (%RCX,%RAX,1),%ZMM6 [6] |
0x5a1ca2 KMOVB %K0,%K4 |
0x5a1ca6 VMOVDQU64 0x40(%RCX,%RAX,1),%ZMM11 [6] |
0x5a1cae KMOVB %K0,%K2 |
0x5a1cb2 VMOVDQU64 0x80(%RCX,%RAX,1),%ZMM12 [6] |
0x5a1cba KMOVB %K0,%K1 |
0x5a1cbe VMOVDQU64 0xc0(%RCX,%RAX,1),%ZMM4 [6] |
0x5a1cc6 KMOVB %K0,%K5 |
0x5a1cca VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} [8] |
0x5a1cd1 VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} [3] |
0x5a1cd8 VMOVDQU64 0x100(%RCX,%RAX,1),%ZMM13 [6] |
0x5a1ce0 KMOVB %K0,%K6 |
0x5a1ce4 VFNMADD231PD (%R9,%RAX,1),%ZMM14,%ZMM0 [4] |
0x5a1ceb VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} [10] |
0x5a1cf2 VMOVDQU64 0x140(%RCX,%RAX,1),%ZMM1 [6] |
0x5a1cfa KMOVB %K0,%K3 |
0x5a1cfe VGATHERQPD (%RBX,%ZMM13,8),%ZMM10{%K6} [1] |
0x5a1d05 VMOVDQU64 0x180(%RCX,%RAX,1),%ZMM3 [6] |
0x5a1d0d KMOVB %K0,%K7 |
0x5a1d11 VMOVDQU64 0x1c0(%RCX,%RAX,1),%ZMM8 [6] |
0x5a1d19 VGATHERQPD (%RBX,%ZMM1,8),%ZMM9{%K3} [7] |
0x5a1d20 KMOVB %K0,%K4 |
0x5a1d24 VGATHERQPD (%RBX,%ZMM3,8),%ZMM15{%K7} [2] |
0x5a1d2b VFNMADD231PD 0x40(%R9,%RAX,1),%ZMM7,%ZMM0 [4] |
0x5a1d33 VFNMADD132PD 0x80(%R9,%RAX,1),%ZMM0,%ZMM2 [4] |
0x5a1d3b VGATHERQPD (%RBX,%ZMM4,8),%ZMM0{%K5} [5] |
0x5a1d42 VFNMADD132PD 0xc0(%R9,%RAX,1),%ZMM2,%ZMM0 [4] |
0x5a1d4a VFNMADD132PD 0x100(%R9,%RAX,1),%ZMM0,%ZMM10 [4] |
0x5a1d52 VGATHERQPD (%RBX,%ZMM8,8),%ZMM0{%K4} [9] |
0x5a1d59 VFNMADD132PD 0x140(%R9,%RAX,1),%ZMM10,%ZMM9 [4] |
0x5a1d61 VFNMADD132PD 0x180(%R9,%RAX,1),%ZMM9,%ZMM15 [4] |
0x5a1d69 VFNMADD132PD 0x1c0(%R9,%RAX,1),%ZMM15,%ZMM0 [4] |
0x5a1d71 ADD $0x200,%RAX |
0x5a1d77 CMP %RAX,%R10 |
0x5a1d7a JNE 5a1c9b |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 310 - 312 |
-------------------------------------------------------------------------------- |
310: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
311: { |
312: tempx -= A_data[jj] * x_data[A_j[jj]]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.45 |
| Bottlenecks | |
| Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
| Source | csr_matvec.c:310-312 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 58.00 |
| CQA cycles if no scalar integer | 58.00 |
| CQA cycles if FP arith vectorized | 58.00 |
| CQA cycles if fully vectorized | 58.00 |
| Front-end cycles | 16.50 |
| DIV/SQRT cycles | 16.00 |
| P0 cycles | 4.00 |
| P1 cycles | 40.00 |
| P2 cycles | 40.00 |
| P3 cycles | 0.00 |
| P4 cycles | 16.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 58 |
| FE+BE cycles (UFS) | 102.55 |
| Stall cycles (UFS) | 89.69 |
| Nb insns | 35.00 |
| Nb uops | 58.00 |
| Nb loads | 24.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.21 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 64.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 26.48 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1536.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 8.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.45 |
| Bottlenecks | |
| Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
| Source | csr_matvec.c:310-312 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 58.00 |
| CQA cycles if no scalar integer | 58.00 |
| CQA cycles if FP arith vectorized | 58.00 |
| CQA cycles if fully vectorized | 58.00 |
| Front-end cycles | 16.50 |
| DIV/SQRT cycles | 16.00 |
| P0 cycles | 4.00 |
| P1 cycles | 40.00 |
| P2 cycles | 40.00 |
| P3 cycles | 0.00 |
| P4 cycles | 16.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 58 |
| FE+BE cycles (UFS) | 102.55 |
| Stall cycles (UFS) | 89.69 |
| Nb insns | 35.00 |
| Nb uops | 58.00 |
| Nb loads | 24.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.21 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 64.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 26.48 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1536.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 8.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
| Source file and lines | csr_matvec.c:310-312 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 58 |
| loop length | 229 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 15 |
| nb stack references | 0 |
| micro-operation queue | 16.50 cycles |
| front end | 16.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 16.00 | 1.00 | 40.00 | 40.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| cycles | 16.00 | 4.00 | 40.00 | 40.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 58.00 |
| FE+BE cycles | 102.55 |
| Stall cycles | 89.69 |
| LB full (events) | 93.20 |
| Front-end | 16.50 |
| Dispatch | 40.00 |
| Data deps. | 58.00 |
| Overall L1 | 58.00 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 (%RCX,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x40(%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x80(%RCX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0xc0(%RCX,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x100(%RCX,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VFNMADD231PD (%R9,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x140(%RCX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM13,8),%ZMM10{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x180(%RCX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x1c0(%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VGATHERQPD (%RBX,%ZMM1,8),%ZMM9{%K3} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM3,8),%ZMM15{%K7} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD231PD 0x40(%R9,%RAX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x80(%R9,%RAX,1),%ZMM0,%ZMM2 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM4,8),%ZMM0{%K5} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD132PD 0xc0(%R9,%RAX,1),%ZMM2,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x100(%R9,%RAX,1),%ZMM0,%ZMM10 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM8,8),%ZMM0{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD132PD 0x140(%R9,%RAX,1),%ZMM10,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x180(%R9,%RAX,1),%ZMM9,%ZMM15 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x1c0(%R9,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RAX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 5a1c9b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_CSRMatrixMatvecOutOfPlace._omp_fn.6 |
| Source file and lines | csr_matvec.c:310-312 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 58 |
| loop length | 229 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 15 |
| nb stack references | 0 |
| micro-operation queue | 16.50 cycles |
| front end | 16.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 16.00 | 1.00 | 40.00 | 40.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| cycles | 16.00 | 4.00 | 40.00 | 40.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 58.00 |
| FE+BE cycles | 102.55 |
| Stall cycles | 89.69 |
| LB full (events) | 93.20 |
| Front-end | 16.50 |
| Dispatch | 40.00 |
| Data deps. | 58.00 |
| Overall L1 | 58.00 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 (%RCX,%RAX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x40(%RCX,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x80(%RCX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0xc0(%RCX,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K5 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM6,8),%ZMM14{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VGATHERQPD (%RBX,%ZMM11,8),%ZMM7{%K2} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x100(%RCX,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VFNMADD231PD (%R9,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM12,8),%ZMM2{%K1} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x140(%RCX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM13,8),%ZMM10{%K6} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VMOVDQU64 0x180(%RCX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| KMOVB %K0,%K7 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VMOVDQU64 0x1c0(%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VGATHERQPD (%RBX,%ZMM1,8),%ZMM9{%K3} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| KMOVB %K0,%K4 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (%RBX,%ZMM3,8),%ZMM15{%K7} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD231PD 0x40(%R9,%RAX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x80(%R9,%RAX,1),%ZMM0,%ZMM2 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM4,8),%ZMM0{%K5} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD132PD 0xc0(%R9,%RAX,1),%ZMM2,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x100(%R9,%RAX,1),%ZMM0,%ZMM10 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VGATHERQPD (%RBX,%ZMM8,8),%ZMM0{%K4} | 4 | 1 | 0 | 4 | 4 | 0 | 1 | 0 | 0 | 21 | 5 |
| VFNMADD132PD 0x140(%R9,%RAX,1),%ZMM10,%ZMM9 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x180(%R9,%RAX,1),%ZMM9,%ZMM15 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VFNMADD132PD 0x1c0(%R9,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x200,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RAX,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 5a1c9b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
