| Loop Id: 484 | Module: exec | Source: par_interp.c:3180-3187 | Coverage: 0.01% |
|---|
| Loop Id: 484 | Module: exec | Source: par_interp.c:3180-3187 | Coverage: 0.01% |
|---|
0x4314b0 MOV -0x48(%RBP),%RAX [3] |
0x4314b4 ADD %RBX,%RAX |
0x4314b7 INC %RAX |
0x4314ba INC %RBX |
0x4314bd CMP $0x1,%RAX |
0x4314c1 JE 431424 |
0x4314c7 VMOVSD (%R15,%RBX,8),%XMM0 [2] |
0x4314cd VMOVUPD -0x60(%RBP),%XMM2 [3] |
0x4314d2 VANDPD %XMM2,%XMM0,%XMM0 |
0x4314d6 VMOVSD (%R15,%R12,8),%XMM1 [1] |
0x4314dc VANDPD %XMM2,%XMM1,%XMM1 |
0x4314e0 VUCOMISD %XMM1,%XMM0 |
0x4314e4 JBE 4314b0 |
0x4314e6 INC %R13 |
0x4314e9 MOV -0x30(%RBP),%RDI [3] |
0x4314ed MOV %R15,%RSI |
0x4314f0 MOV %R13,%RDX |
0x4314f3 MOV %RBX,%RCX |
0x4314f6 CALL 4ddf60 <hypre_swap2> |
0x4314fb JMP 4314b0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_interp.c: 3180 - 3187 |
-------------------------------------------------------------------------------- |
3180: if (left >= right) |
3181: return; |
3182: hypre_swap2( v, w, left, (left+right)/2); |
3183: last = left; |
3184: for (i = left+1; i <= right; i++) |
3185: if (fabs(w[i]) > fabs(w[left])) |
3186: { |
3187: hypre_swap2(v, w, ++last, i); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_qsort2abs | par_interp.c:3191 | exec |
| ○ | hypre_BoomerAMGInterpTruncatio[...] | par_interp.c:2912 | exec |
| ○ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_BoomerAMGInterpTruncatio[...] | par_interp.c:2726 | exec |
| ○ | hypre_BoomerAMGBuildExtPIInter[...] | par_lr_interp.c:1799 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:847 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.62 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 7.55 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.62 |
| Bottlenecks | |
| Function | hypre_qsort2abs |
| Source | par_interp.c:3180-3187 |
| Source loop unroll info | unrolled by 15 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | peel/tail |
| Unroll factor | 1 |
| CQA cycles | 4.25 |
| CQA cycles if no scalar integer | 2.63 |
| CQA cycles if FP arith vectorized | 4.25 |
| CQA cycles if fully vectorized | 0.56 |
| Front-end cycles | 4.25 |
| DIV/SQRT cycles | 2.63 |
| P0 cycles | 2.63 |
| P1 cycles | 2.25 |
| P2 cycles | 2.25 |
| P3 cycles | 0.50 |
| P4 cycles | 2.63 |
| P5 cycles | 2.63 |
| P6 cycles | 0.50 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 4.28 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 16.50 |
| Nb uops | 17.00 |
| Nb loads | 4.50 |
| Nb stores | 0.00 |
| Nb stack references | 2.50 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.73 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 44.00 |
| Bytes stored | 0.00 |
| Stride 0 | 2.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 35.71 |
| Vectorization ratio load | 26.67 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 47.62 |
| Vector-efficiency ratio all | 16.96 |
| Vector-efficiency ratio load | 15.83 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.45 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.33 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 7.62 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.75 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_qsort2abs |
| Source | par_interp.c:3180-3187 |
| Source loop unroll info | unrolled by 15 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | peel/tail |
| Unroll factor | 1 |
| CQA cycles | 5.25 |
| CQA cycles if no scalar integer | 2.25 |
| CQA cycles if FP arith vectorized | 5.25 |
| CQA cycles if fully vectorized | 0.69 |
| Front-end cycles | 5.25 |
| DIV/SQRT cycles | 3.00 |
| P0 cycles | 3.00 |
| P1 cycles | 2.50 |
| P2 cycles | 2.50 |
| P3 cycles | 1.00 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 5.13 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 20.00 |
| Nb uops | 21.00 |
| Nb loads | 5.00 |
| Nb stores | 0.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 9.14 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 0.00 |
| Stride 0 | 2.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 21.43 |
| Vectorization ratio load | 20.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 28.57 |
| Vector-efficiency ratio all | 15.18 |
| Vector-efficiency ratio load | 15.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 16.07 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.08 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 7.43 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.44 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_qsort2abs |
| Source | par_interp.c:3180-3187 |
| Source loop unroll info | unrolled by 15 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | peel/tail |
| Unroll factor | 1 |
| CQA cycles | 3.25 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 3.25 |
| CQA cycles if fully vectorized | 0.44 |
| Front-end cycles | 3.25 |
| DIV/SQRT cycles | 2.25 |
| P0 cycles | 2.25 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 0.00 |
| P4 cycles | 2.25 |
| P5 cycles | 2.25 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.42 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 13.00 |
| Nb uops | 13.00 |
| Nb loads | 4.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.31 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 40.00 |
| Bytes stored | 0.00 |
| Stride 0 | 2.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 50.00 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 66.67 |
| Vector-efficiency ratio all | 18.75 |
| Vector-efficiency ratio load | 16.67 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 20.83 |
| Path / |
| Function | hypre_qsort2abs |
| Source file and lines | par_interp.c:3180-3187 |
| Module | exec |
| nb instructions | 16.50 |
| nb uops | 17 |
| loop length | 65.50 |
| used x86 registers | 7.50 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2.50 |
| micro-operation queue | 4.25 cycles |
| front end | 4.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.63 | 2.63 | 2.25 | 2.25 | 0.50 | 2.63 | 2.63 | 0.50 |
| cycles | 2.63 | 2.63 | 2.25 | 2.25 | 0.50 | 2.63 | 2.63 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 4.28 |
| Stall cycles | 0.00 |
| Front-end | 4.25 |
| Dispatch | 2.63 |
| Data deps. | 1.00 |
| Overall L1 | 4.25 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | 33% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 66% |
| all | 35% |
| load | 26% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 47% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 18% |
| load | 16% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 16% |
| load | 15% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Function | hypre_qsort2abs |
| Source file and lines | par_interp.c:3180-3187 |
| Module | exec |
| nb instructions | 20 |
| nb uops | 21 |
| loop length | 77 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 5.25 cycles |
| front end | 5.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 2.50 | 2.50 | 1.00 | 3.00 | 3.00 | 1.00 |
| cycles | 3.00 | 3.00 | 2.50 | 2.50 | 1.00 | 3.00 | 3.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 5.13 |
| Stall cycles | 0.00 |
| Front-end | 5.25 |
| Dispatch | 3.00 |
| Data deps. | 1.00 |
| Overall L1 | 5.25 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | 33% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 66% |
| all | 21% |
| load | 20% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 28% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 18% |
| load | 16% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| all | 15% |
| load | 15% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD %RBX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| INC %RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP $0x1,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 431424 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%R15,%RBX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVUPD -0x60(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM2,%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVSD (%R15,%R12,8),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM2,%XMM1,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VUCOMISD %XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4314b0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| INC %R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV -0x30(%RBP),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R15,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %RBX,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| CALL 4ddf60 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| JMP 4314b0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_qsort2abs |
| Source file and lines | par_interp.c:3180-3187 |
| Module | exec |
| nb instructions | 13 |
| nb uops | 13 |
| loop length | 54 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 3.25 cycles |
| front end | 3.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.25 | 2.25 | 2.00 | 2.00 | 0.00 | 2.25 | 2.25 | 0.00 |
| cycles | 2.25 | 2.25 | 2.00 | 2.00 | 0.00 | 2.25 | 2.25 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.42 |
| Stall cycles | 0.00 |
| Front-end | 3.25 |
| Dispatch | 2.25 |
| Data deps. | 1.00 |
| Overall L1 | 3.25 |
| all | 50% |
| load | 33% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 66% |
| all | 18% |
| load | 16% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 20% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD %RBX,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| INC %RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP $0x1,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 431424 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%R15,%RBX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVUPD -0x60(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM2,%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VMOVSD (%R15,%R12,8),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VANDPD %XMM2,%XMM1,%XMM1 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 1 | 0.33 |
| VUCOMISD %XMM1,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| JBE 4314b0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
