| Loop Id: 1185 | Module: exec | Source: par_lr_interp.c:1644-1650 | Coverage: 0.14% |
|---|
| Loop Id: 1185 | Module: exec | Source: par_lr_interp.c:1644-1650 | Coverage: 0.14% |
|---|
0x453450 INC %R10 |
0x453453 CMP %R10,%R9 |
0x453456 JE 4534d4 |
0x453458 MOV (%R12,%R10,8),%RAX [1] |
0x45345c MOV -0x38(%RBP),%RCX [5] |
0x453460 MOV (%RCX,%RAX,8),%RCX [4] |
0x453464 CMP %R13,%RCX |
0x453467 JL 45348e |
0x453469 VMOVSD (%RBX,%R10,8),%XMM4 [6] |
0x45346f VMULSD %XMM5,%XMM4,%XMM1 |
0x453473 VUCOMISD %XMM0,%XMM1 |
0x453477 JAE 45348e |
0x453479 MOV -0xb8(%RBP),%RSI [5] |
0x453480 MOV (%RSI),%RSI [2] |
0x453483 VFMADD213SD (%RSI,%RCX,8),%XMM3,%XMM4 [3] |
0x453489 VMOVSD %XMM4,(%RSI,%RCX,8) [3] |
0x45348e CMP %RDI,%RAX |
0x453491 JNE 453450 |
0x453493 VMOVSD (%RBX,%R10,8),%XMM1 [6] |
0x453499 VMULSD %XMM5,%XMM1,%XMM4 |
0x45349d VMULSD %XMM3,%XMM1,%XMM1 |
0x4534a1 VCMPSD $0x1,%XMM0,%XMM4,%K1 |
0x4534a8 VMOVAPD %XMM15,%XMM4 |
0x4534ac VMOVSD %XMM1,%XMM4,%XMM4{%K1} |
0x4534b2 VADDSD %XMM6,%XMM4,%XMM6 |
0x4534b6 JMP 453450 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_lr_interp.c: 1644 - 1650 |
-------------------------------------------------------------------------------- |
1644: for(jj1 = A_diag_i[i1]+1; jj1 < A_diag_i[i1+1]; jj1++) |
1645: { |
1646: i2 = A_diag_j[jj1]; |
1647: if(P_marker[i2] >= jj_begin_row && (sgn*A_diag_data[jj1]) < 0) |
1648: P_diag_data[P_marker[i2]] += |
1649: distribute*A_diag_data[jj1]; |
1650: if(i2 == i && (sgn*A_diag_data[jj1]) < 0) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_BoomerAMGBuildExtPIInter[...] | par_lr_interp.c:1196 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:847 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.42 |
| CQA speedup if FP arith vectorized | 2.65 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.59 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
| Source | par_lr_interp.c:1644-1650 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 4.75 |
| CQA cycles if FP arith vectorized | 2.55 |
| CQA cycles if fully vectorized | 0.84 |
| Front-end cycles | 6.75 |
| DIV/SQRT cycles | 4.25 |
| P0 cycles | 4.25 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 1.00 |
| P4 cycles | 4.25 |
| P5 cycles | 4.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 7.00 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 26.00 |
| Nb uops | 26.00 |
| Nb loads | 8.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.89 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 3.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 7.14 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 16.67 |
| Vector-efficiency ratio all | 13.39 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 14.58 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.42 |
| CQA speedup if FP arith vectorized | 2.65 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.59 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
| Source | par_lr_interp.c:1644-1650 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 4.75 |
| CQA cycles if FP arith vectorized | 2.55 |
| CQA cycles if fully vectorized | 0.84 |
| Front-end cycles | 6.75 |
| DIV/SQRT cycles | 4.25 |
| P0 cycles | 4.25 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 1.00 |
| P4 cycles | 4.25 |
| P5 cycles | 4.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 7.00 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 26.00 |
| Nb uops | 26.00 |
| Nb loads | 8.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.89 |
| Nb FLOP add-sub | 1.00 |
| Nb FLOP mul | 3.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 64.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 7.14 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 16.67 |
| Vector-efficiency ratio all | 13.39 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 14.58 |
| Path / |
| Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
| Source file and lines | par_lr_interp.c:1644-1650 |
| Module | exec |
| nb instructions | 26 |
| nb uops | 26 |
| loop length | 104 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 0.33 |
| micro-operation queue | 6.75 cycles |
| front end | 6.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.25 | 4.25 | 4.00 | 4.00 | 1.00 | 4.25 | 4.25 | 1.00 |
| cycles | 4.25 | 4.25 | 4.00 | 4.00 | 1.00 | 4.25 | 4.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 7.00 |
| Stall cycles | 0.00 |
| Front-end | 6.75 |
| Dispatch | 4.25 |
| Overall L1 | 6.75 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 8% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| INC %R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R10,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4534d4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%R12,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R13,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JL 45348e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%R10,8),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD %XMM5,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| JAE 45348e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RSI),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RSI,%RCX,8),%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM4,(%RSI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 453450 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD %XMM5,%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPSD $0x1,%XMM0,%XMM4,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VMOVAPD %XMM15,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVSD %XMM1,%XMM4,%XMM4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM6,%XMM4,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JMP 453450 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_BoomerAMGBuildExtPIInterp.extracted |
| Source file and lines | par_lr_interp.c:1644-1650 |
| Module | exec |
| nb instructions | 26 |
| nb uops | 26 |
| loop length | 104 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 0.33 |
| micro-operation queue | 6.75 cycles |
| front end | 6.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.25 | 4.25 | 4.00 | 4.00 | 1.00 | 4.25 | 4.25 | 1.00 |
| cycles | 4.25 | 4.25 | 4.00 | 4.00 | 1.00 | 4.25 | 4.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 7.00 |
| Stall cycles | 0.00 |
| Front-end | 6.75 |
| Dispatch | 4.25 |
| Overall L1 | 6.75 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 8% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| INC %R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R10,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4534d4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%R12,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x38(%RBP),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RCX,%RAX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R13,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JL 45348e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%R10,8),%XMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD %XMM5,%XMM4,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUCOMISD %XMM0,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| JAE 45348e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xb8(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RSI),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RSI,%RCX,8),%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM4,(%RSI,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 453450 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RBX,%R10,8),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD %XMM5,%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM3,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPSD $0x1,%XMM0,%XMM4,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VMOVAPD %XMM15,%XMM4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVSD %XMM1,%XMM4,%XMM4{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM6,%XMM4,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JMP 453450 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
