| Loop Id: 665 | Module: exec | Source: par_multi_interp.c:1811-1837 | Coverage: 2.01% |
|---|
| Loop Id: 665 | Module: exec | Source: par_multi_interp.c:1811-1837 | Coverage: 2.01% |
|---|
0x472200 MOV 0x120(%RSP),%R8 |
0x472208 MOV 0x168(%RSP),%R14 |
0x472210 MOV (%R8,%RCX,8),%RCX |
0x472214 CMP %RCX,(%R8,%R14,1) |
0x472218 JE 47225e |
0x47221a ADD $0x8,%RSI |
0x47221e ADD $0x8,%RAX |
0x472222 CMP %RSI,%R9 |
0x472225 JE 47226f |
0x472227 MOV (%RSI),%RCX |
0x47222a MOV 0x170(%RSP),%R14 |
0x472232 LEA (,%RCX,8),%R8 |
0x47223a CMP (%R14,%RCX,8),%RDI |
0x47223e JE 4723d0 |
0x472244 MOV 0x128(%RSP),%RDX |
0x47224c CMPQ $-0x3,(%RDX,%RCX,8) |
0x472251 JE 47221a |
0x472253 CMPQ $0x1,0x160(%RSP) |
0x47225c JNE 472200 |
0x47225e ADD $0x8,%RSI |
0x472262 VADDSD (%RAX),%XMM0,%XMM0 |
0x472266 ADD $0x8,%RAX |
0x47226a CMP %RSI,%R9 |
0x47226d JNE 472227 |
0x4723d0 MOV 0xf0(%RSP),%R14 |
0x4723d8 MOV (%R14,%RCX,8),%RDX |
0x4723dc MOV 0x8(%R14,%R8,1),%R14 |
0x4723e1 MOV %R14,0x178(%RSP) |
0x4723e9 CMP %R14,%RDX |
0x4723ec JGE 472568 |
0x4723f2 SUB %RDX,%R14 |
0x4723f5 AND $0x3,%R14D |
0x4723f9 JE 4724a4 |
0x4723ff CMP $0x1,%R14 |
0x472403 JE 472465 |
0x472405 CMP $0x2,%R14 |
0x472409 JE 472437 |
0x47240b VMOVSD (%RAX),%XMM5 |
0x47240f MOV (%R13,%RDX,8),%R14 |
0x472414 VMULSD (%R12,%RDX,8),%XMM5,%XMM6 |
0x47241a MOV (%R15,%R14,8),%R14 |
0x47241e INC %RDX |
0x472421 LEA (%R12,%R14,8),%R14 |
0x472425 VADDSD (%R14),%XMM6,%XMM7 |
0x47242a VADDSD %XMM6,%XMM1,%XMM1 |
0x47242e VADDSD %XMM6,%XMM0,%XMM0 |
0x472432 VMOVSD %XMM7,(%R14) |
0x472437 VMOVSD (%RAX),%XMM8 |
0x47243b MOV (%R13,%RDX,8),%R14 |
0x472440 VMULSD (%R12,%RDX,8),%XMM8,%XMM9 |
0x472446 MOV (%R15,%R14,8),%R14 |
0x47244a INC %RDX |
0x47244d LEA (%R12,%R14,8),%R14 |
0x472451 VADDSD (%R14),%XMM9,%XMM10 |
0x472456 VADDSD %XMM9,%XMM1,%XMM1 |
0x47245b VADDSD %XMM9,%XMM0,%XMM0 |
0x472460 VMOVSD %XMM10,(%R14) |
0x472465 VMOVSD (%RAX),%XMM11 |
0x472469 MOV (%R13,%RDX,8),%R14 |
0x47246e VMULSD (%R12,%RDX,8),%XMM11,%XMM12 |
0x472474 MOV (%R15,%R14,8),%R14 |
0x472478 INC %RDX |
0x47247b LEA (%R12,%R14,8),%R14 |
0x47247f VADDSD (%R14),%XMM12,%XMM13 |
0x472484 VADDSD %XMM12,%XMM1,%XMM1 |
0x472489 VADDSD %XMM12,%XMM0,%XMM0 |
0x47248e VMOVSD %XMM13,(%R14) |
0x472493 MOV 0x178(%RSP),%R14 |
0x47249b CMP %R14,%RDX |
0x47249e JE 472568 |
(667) 0x4724a4 VMOVSD (%RAX),%XMM14 |
(667) 0x4724a8 MOV (%R13,%RDX,8),%R14 |
(667) 0x4724ad VMULSD (%R12,%RDX,8),%XMM14,%XMM15 |
(667) 0x4724b3 MOV (%R15,%R14,8),%R14 |
(667) 0x4724b7 LEA (%R12,%R14,8),%R14 |
(667) 0x4724bb VADDSD (%R14),%XMM15,%XMM2 |
(667) 0x4724c0 VADDSD %XMM15,%XMM1,%XMM6 |
(667) 0x4724c5 VADDSD %XMM15,%XMM0,%XMM7 |
(667) 0x4724ca VMOVSD %XMM2,(%R14) |
(667) 0x4724cf MOV 0x8(%R13,%RDX,8),%R14 |
(667) 0x4724d4 VMOVSD (%RAX),%XMM5 |
(667) 0x4724d8 MOV (%R15,%R14,8),%R14 |
(667) 0x4724dc VMULSD 0x8(%R12,%RDX,8),%XMM5,%XMM8 |
(667) 0x4724e3 LEA (%R12,%R14,8),%R14 |
(667) 0x4724e7 VADDSD (%R14),%XMM8,%XMM9 |
(667) 0x4724ec VADDSD %XMM8,%XMM6,%XMM10 |
(667) 0x4724f1 VADDSD %XMM8,%XMM7,%XMM11 |
(667) 0x4724f6 VMOVSD %XMM9,(%R14) |
(667) 0x4724fb MOV 0x10(%R13,%RDX,8),%R14 |
(667) 0x472500 VMOVSD (%RAX),%XMM12 |
(667) 0x472504 MOV (%R15,%R14,8),%R14 |
(667) 0x472508 VMULSD 0x10(%R12,%RDX,8),%XMM12,%XMM13 |
(667) 0x47250f LEA (%R12,%R14,8),%R14 |
(667) 0x472513 VADDSD (%R14),%XMM13,%XMM1 |
(667) 0x472518 VADDSD %XMM13,%XMM10,%XMM14 |
(667) 0x47251d VADDSD %XMM13,%XMM11,%XMM0 |
(667) 0x472522 VMOVSD %XMM1,(%R14) |
(667) 0x472527 MOV 0x18(%R13,%RDX,8),%R14 |
(667) 0x47252c VMOVSD (%RAX),%XMM15 |
(667) 0x472530 MOV (%R15,%R14,8),%R14 |
(667) 0x472534 VMULSD 0x18(%R12,%RDX,8),%XMM15,%XMM12 |
(667) 0x47253b ADD $0x4,%RDX |
(667) 0x47253f LEA (%R12,%R14,8),%R14 |
(667) 0x472543 VADDSD (%R14),%XMM12,%XMM2 |
(667) 0x472548 VADDSD %XMM12,%XMM14,%XMM1 |
(667) 0x47254d VADDSD %XMM12,%XMM0,%XMM0 |
(667) 0x472552 VMOVSD %XMM2,(%R14) |
(667) 0x472557 MOV 0x178(%RSP),%R14 |
(667) 0x47255f CMP %R14,%RDX |
(667) 0x472562 JNE 4724a4 |
0x472568 MOV 0xf8(%RSP),%R14 |
0x472570 MOV (%R14,%RCX,8),%RDX |
0x472574 MOV 0x8(%R14,%R8,1),%R8 |
0x472579 CMP %R8,%RDX |
0x47257c JGE 47221a |
0x472582 MOV %R8,%RCX |
0x472585 SUB %RDX,%RCX |
0x472588 AND $0x3,%ECX |
0x47258b JE 472629 |
0x472591 CMP $0x1,%RCX |
0x472595 JE 4725f3 |
0x472597 CMP $0x2,%RCX |
0x47259b JE 4725c8 |
0x47259d VMOVSD (%RAX),%XMM6 |
0x4725a1 MOV (%R10,%RDX,8),%R14 |
0x4725a5 VMULSD (%R11,%RDX,8),%XMM6,%XMM7 |
0x4725ab MOV (%RBX,%R14,8),%RCX |
0x4725af INC %RDX |
0x4725b2 LEA (%R11,%RCX,8),%R14 |
0x4725b6 VADDSD (%R14),%XMM7,%XMM5 |
0x4725bb VADDSD %XMM7,%XMM1,%XMM1 |
0x4725bf VADDSD %XMM7,%XMM0,%XMM0 |
0x4725c3 VMOVSD %XMM5,(%R14) |
0x4725c8 VMOVSD (%RAX),%XMM8 |
0x4725cc MOV (%R10,%RDX,8),%RCX |
0x4725d0 VMULSD (%R11,%RDX,8),%XMM8,%XMM9 |
0x4725d6 MOV (%RBX,%RCX,8),%R14 |
0x4725da INC %RDX |
0x4725dd LEA (%R11,%R14,8),%RCX |
0x4725e1 VADDSD (%RCX),%XMM9,%XMM10 |
0x4725e5 VADDSD %XMM9,%XMM1,%XMM1 |
0x4725ea VADDSD %XMM9,%XMM0,%XMM0 |
0x4725ef VMOVSD %XMM10,(%RCX) |
0x4725f3 VMOVSD (%RAX),%XMM11 |
0x4725f7 MOV (%R10,%RDX,8),%R14 |
0x4725fb VMULSD (%R11,%RDX,8),%XMM11,%XMM12 |
0x472601 MOV (%RBX,%R14,8),%RCX |
0x472605 INC %RDX |
0x472608 LEA (%R11,%RCX,8),%R14 |
0x47260c VADDSD (%R14),%XMM12,%XMM13 |
0x472611 VADDSD %XMM12,%XMM1,%XMM1 |
0x472616 VADDSD %XMM12,%XMM0,%XMM0 |
0x47261b VMOVSD %XMM13,(%R14) |
0x472620 CMP %R8,%RDX |
0x472623 JE 47221a |
(666) 0x472629 VMOVSD (%RAX),%XMM12 |
(666) 0x47262d MOV (%R10,%RDX,8),%RCX |
(666) 0x472631 VMULSD (%R11,%RDX,8),%XMM12,%XMM14 |
(666) 0x472637 MOV (%RBX,%RCX,8),%R14 |
(666) 0x47263b LEA (%R11,%R14,8),%RCX |
(666) 0x47263f MOV 0x8(%R10,%RDX,8),%R14 |
(666) 0x472644 VADDSD (%RCX),%XMM14,%XMM15 |
(666) 0x472648 VADDSD %XMM14,%XMM1,%XMM1 |
(666) 0x47264d VADDSD %XMM14,%XMM0,%XMM0 |
(666) 0x472652 VMOVSD %XMM15,(%RCX) |
(666) 0x472656 MOV (%RBX,%R14,8),%RCX |
(666) 0x47265a VMOVSD (%RAX),%XMM2 |
(666) 0x47265e LEA (%R11,%RCX,8),%R14 |
(666) 0x472662 MOV 0x10(%R10,%RDX,8),%RCX |
(666) 0x472667 VMULSD 0x8(%R11,%RDX,8),%XMM2,%XMM6 |
(666) 0x47266e VADDSD (%R14),%XMM6,%XMM7 |
(666) 0x472673 VADDSD %XMM6,%XMM1,%XMM8 |
(666) 0x472677 VADDSD %XMM6,%XMM0,%XMM9 |
(666) 0x47267b VMOVSD %XMM7,(%R14) |
(666) 0x472680 MOV (%RBX,%RCX,8),%R14 |
(666) 0x472684 VMOVSD (%RAX),%XMM5 |
(666) 0x472688 LEA (%R11,%R14,8),%RCX |
(666) 0x47268c MOV 0x18(%R10,%RDX,8),%R14 |
(666) 0x472691 VMULSD 0x10(%R11,%RDX,8),%XMM5,%XMM10 |
(666) 0x472698 VADDSD (%RCX),%XMM10,%XMM11 |
(666) 0x47269c VADDSD %XMM10,%XMM8,%XMM13 |
(666) 0x4726a1 VADDSD %XMM10,%XMM9,%XMM14 |
(666) 0x4726a6 VMOVSD %XMM11,(%RCX) |
(666) 0x4726aa MOV (%RBX,%R14,8),%RCX |
(666) 0x4726ae VMOVSD (%RAX),%XMM12 |
(666) 0x4726b2 LEA (%R11,%RCX,8),%R14 |
(666) 0x4726b6 VMULSD 0x18(%R11,%RDX,8),%XMM12,%XMM12 |
(666) 0x4726bd ADD $0x4,%RDX |
(666) 0x4726c1 VADDSD (%R14),%XMM12,%XMM15 |
(666) 0x4726c6 VADDSD %XMM12,%XMM13,%XMM1 |
(666) 0x4726cb VADDSD %XMM12,%XMM14,%XMM0 |
(666) 0x4726d0 VMOVSD %XMM15,(%R14) |
(666) 0x4726d5 CMP %R8,%RDX |
(666) 0x4726d8 JNE 472629 |
0x4726de JMP 47221a |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 1811 - 1837 |
-------------------------------------------------------------------------------- |
1811: for (j=A_diag_i[i1]+1; j < A_diag_i[i1+1]; j++) |
1812: { |
1813: j1 = A_diag_j[j]; |
1814: if (tmp_marker[j1] == i1) |
1815: { |
1816: for (k=P_diag_i[j1]; k < P_diag_i[j1+1]; k++) |
1817: { |
1818: k1 = P_diag_j[k]; |
1819: alfa = A_diag_data[j]*P_diag_data[k]; |
1820: P_diag_data[tmp_array[k1]] += alfa; |
1821: sum_C += alfa; |
1822: sum_N += alfa; |
1823: } |
1824: for (k=P_offd_i[j1]; k < P_offd_i[j1+1]; k++) |
1825: { |
1826: k1 = P_offd_j[k]; |
1827: alfa = A_diag_data[j]*P_offd_data[k]; |
1828: P_offd_data[tmp_array_offd[k1]] += alfa; |
1829: sum_C += alfa; |
1830: sum_N += alfa; |
1831: } |
1832: } |
1833: else |
1834: { |
1835: if (CF_marker[j1] != -3 && |
1836: (num_functions == 1 || dof_func[i1] == dof_func[j1])) |
1837: sum_N += A_diag_data[j]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.75 |
| CQA speedup if FP arith vectorized | 2.37 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.29 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
| Source | par_multi_interp.c:1811-1837 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 31.00 |
| CQA cycles if no scalar integer | 17.75 |
| CQA cycles if FP arith vectorized | 13.06 |
| CQA cycles if fully vectorized | 3.88 |
| Front-end cycles | 31.00 |
| DIV/SQRT cycles | 19.25 |
| P0 cycles | 19.25 |
| P1 cycles | 24.00 |
| P2 cycles | 24.00 |
| P3 cycles | 7.00 |
| P4 cycles | 19.25 |
| P5 cycles | 19.25 |
| P6 cycles | 7.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 31.35 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 116.00 |
| Nb uops | 116.00 |
| Nb loads | 48.00 |
| Nb stores | 7.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 0.81 |
| Nb FLOP add-sub | 19.00 |
| Nb FLOP mul | 6.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.19 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 384.00 |
| Bytes stored | 56.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.75 |
| CQA speedup if FP arith vectorized | 2.37 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.29 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
| Source | par_multi_interp.c:1811-1837 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 31.00 |
| CQA cycles if no scalar integer | 17.75 |
| CQA cycles if FP arith vectorized | 13.06 |
| CQA cycles if fully vectorized | 3.88 |
| Front-end cycles | 31.00 |
| DIV/SQRT cycles | 19.25 |
| P0 cycles | 19.25 |
| P1 cycles | 24.00 |
| P2 cycles | 24.00 |
| P3 cycles | 7.00 |
| P4 cycles | 19.25 |
| P5 cycles | 19.25 |
| P6 cycles | 7.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 31.35 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 116.00 |
| Nb uops | 116.00 |
| Nb loads | 48.00 |
| Nb stores | 7.00 |
| Nb stack references | 8.00 |
| FLOP/cycle | 0.81 |
| Nb FLOP add-sub | 19.00 |
| Nb FLOP mul | 6.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.19 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 384.00 |
| Bytes stored | 56.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
| Source file and lines | par_multi_interp.c:1811-1837 |
| Module | exec |
| nb instructions | 116 |
| nb uops | 116 |
| loop length | 521 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 11 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 8 |
| ADD-SUB / MUL ratio | 3.17 |
| micro-operation queue | 31.00 cycles |
| front end | 31.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 19.25 | 19.25 | 24.00 | 24.00 | 7.00 | 19.25 | 19.25 | 7.00 |
| cycles | 19.25 | 19.25 | 24.00 | 24.00 | 7.00 | 19.25 | 19.25 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 31.35 |
| Stall cycles | 0.00 |
| Front-end | 31.00 |
| Dispatch | 24.00 |
| Overall L1 | 31.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x120(%RSP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x168(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R8,%RCX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %RCX,(%R8,%R14,1) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 47225e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD $0x8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD $0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 47226f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%RSI),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x170(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA (,%RCX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP (%R14,%RCX,8),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 4723d0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0x128(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMPQ $-0x3,(%RDX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0x1,0x160(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JNE 472200 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD $0x8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VADDSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| ADD $0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 472227 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0xf0(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R8,1),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R14,0x178(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 472568 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| SUB %RDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x3,%R14D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4724a4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472465 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472437 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RAX),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM6,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM6,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM8,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV 0x178(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472568 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0xf8(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R8,1),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %RDX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x3,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472629 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4725f3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4725c8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RAX),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%R14,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%RCX,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM7,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM7,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM7,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM5,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM8,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%RCX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%R14,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%RCX),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%R14,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%RCX,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 47221a | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.10 |
| Source file and lines | par_multi_interp.c:1811-1837 |
| Module | exec |
| nb instructions | 116 |
| nb uops | 116 |
| loop length | 521 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 11 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 8 |
| ADD-SUB / MUL ratio | 3.17 |
| micro-operation queue | 31.00 cycles |
| front end | 31.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 19.25 | 19.25 | 24.00 | 24.00 | 7.00 | 19.25 | 19.25 | 7.00 |
| cycles | 19.25 | 19.25 | 24.00 | 24.00 | 7.00 | 19.25 | 19.25 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 31.35 |
| Stall cycles | 0.00 |
| Front-end | 31.00 |
| Dispatch | 24.00 |
| Overall L1 | 31.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x120(%RSP),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x168(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R8,%RCX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %RCX,(%R8,%R14,1) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 47225e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD $0x8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD $0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 47226f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV (%RSI),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x170(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA (,%RCX,8),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP (%R14,%RCX,8),%RDI | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 4723d0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0x128(%RSP),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMPQ $-0x3,(%RDX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0x1,0x160(%RSP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JNE 472200 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD $0x8,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VADDSD (%RAX),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| ADD $0x8,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 472227 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0xf0(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R8,1),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R14,0x178(%RSP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 472568 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| SUB %RDX,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x3,%R14D | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4724a4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472465 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472437 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RAX),%XMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM6,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM6,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM8,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R13,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R12,%RDX,8),%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%R15,%R14,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R12,%R14,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV 0x178(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R14,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472568 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV 0xf8(%RSP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%RCX,8),%RDX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R8,1),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %RDX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x3,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 472629 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4725f3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4725c8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%RAX),%XMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM6,%XMM7 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%R14,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%RCX,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM7,%XMM5 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM7,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM7,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM5,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM8,%XMM9 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%RCX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%R14,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%RCX),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM9,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM10,(%RCX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VMOVSD (%RAX),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R10,%RDX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMULSD (%R11,%RDX,8),%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| MOV (%RBX,%R14,8),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INC %RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%R11,%RCX,8),%R14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDSD (%R14),%XMM12,%XMM13 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM13,(%R14) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 47221a | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 47221a | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
