| Loop Id: 2474 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.05% |
|---|
| Loop Id: 2474 | Module: exec | Source: par_csr_matop.c:865-989 [...] | Coverage: 0.05% |
|---|
0x55a26d CMPQ $0,-0x118(%RBP) |
0x55a275 MOV -0x40(%RBP),%RSI |
0x55a279 MOV %R12,%RDX |
0x55a27c JNE 55a3c5 |
0x55a282 MOV -0xb0(%RBP),%R11 |
0x55a289 MOV -0xa0(%RBP),%R14 |
0x55a290 MOV (%R11,%R14,8),%RDI |
0x55a294 CMP %RDI,0x8(%R11,%R14,8) |
0x55a299 JLE 55a365 |
0x55a29f MOV -0x128(%RBP),%R11 |
0x55a2a6 MOV -0x130(%RBP),%R13 |
0x55a2ad MOV %RSI,-0xa8(%RBP) |
0x55a2b4 MOV %RDI,-0x48(%RBP) |
0x55a2b8 NOPL (%RAX,%RAX,1) |
(2479) 0x55a2c0 MOV -0x48(%RBP),%R9 |
(2479) 0x55a2c4 MOV -0xc8(%RBP),%RCX |
(2479) 0x55a2cb MOV -0xd0(%RBP),%RSI |
(2479) 0x55a2d2 MOV -0xc0(%RBP),%R10 |
(2479) 0x55a2d9 MOV (%RCX,%R9,8),%RDI |
(2479) 0x55a2dd VMOVSD (%RSI,%R9,8),%XMM7 |
(2479) 0x55a2e3 LEA 0x8(,%RDI,8),%R9 |
(2479) 0x55a2eb MOV (%R10,%RDI,8),%RAX |
(2479) 0x55a2ef LEA (%R10,%R9,1),%R14 |
(2479) 0x55a2f3 MOV (%R14),%R10 |
(2479) 0x55a2f6 CMP %R10,%RAX |
(2479) 0x55a2f9 JGE 55a32f |
(2479) 0x55a2fb NOPL (%RAX,%RAX,1) |
(2481) 0x55a300 MOV (%R11,%RAX,8),%RCX |
(2481) 0x55a304 VMULSD (%R13,%RAX,8),%XMM7,%XMM8 |
(2481) 0x55a30b LEA (%R8,%RCX,8),%RSI |
(2481) 0x55a30f MOV (%RSI),%R15 |
(2481) 0x55a312 CMP %R15,%R12 |
(2481) 0x55a315 JG 55a500 |
(2481) 0x55a31b LEA (%RBX,%R15,8),%RCX |
(2481) 0x55a31f INC %RAX |
(2481) 0x55a322 VADDSD (%RCX),%XMM8,%XMM9 |
(2481) 0x55a326 VMOVSD %XMM9,(%RCX) |
(2481) 0x55a32a CMP %R10,%RAX |
(2481) 0x55a32d JL 55a300 |
(2479) 0x55a32f CMPQ $0,-0xb8(%RBP) |
(2479) 0x55a337 JNE 55a530 |
(2479) 0x55a33d INCQ -0x48(%RBP) |
(2479) 0x55a341 MOV -0xb0(%RBP),%R14 |
(2479) 0x55a348 MOV -0xa0(%RBP),%RSI |
(2479) 0x55a34f MOV -0x48(%RBP),%RAX |
(2479) 0x55a353 CMP %RAX,0x8(%R14,%RSI,8) |
(2479) 0x55a358 JG 55a2c0 |
0x55a35e MOV -0xa8(%RBP),%RSI |
0x55a365 INCQ -0xa0(%RBP) |
0x55a36c MOV -0xa0(%RBP),%R12 |
0x55a373 CMP %R12,-0x120(%RBP) |
0x55a37a JE 55a64f |
0x55a380 CMPQ $0,-0x110(%RBP) |
0x55a388 MOV %RSI,-0x40(%RBP) |
0x55a38c MOV %RDX,%R12 |
0x55a38f JE 55a26d |
0x55a3c5 MOV -0xe0(%RBP),%R15 |
0x55a3cc MOV -0xa0(%RBP),%RAX |
0x55a3d3 MOV (%R15,%RAX,8),%R14 |
0x55a3d7 CMP 0x8(%R15,%RAX,8),%R14 |
0x55a3dc JGE 55a282 |
0x55a3e2 MOV %R12,-0x48(%RBP) |
0x55a3e6 MOV -0x50(%RBP),%R11 |
0x55a3ea MOV %R14,%RDI |
0x55a3ed MOV -0x58(%RBP),%R12 |
0x55a3f1 NOPL (%RAX) |
(2475) 0x55a3f8 MOV -0x100(%RBP),%R13 |
(2475) 0x55a3ff MOV -0xe8(%RBP),%R10 |
(2475) 0x55a406 MOV -0x108(%RBP),%RCX |
(2475) 0x55a40d MOV (%R13,%RDI,8),%R14 |
(2475) 0x55a412 VMOVSD (%RCX,%RDI,8),%XMM2 |
(2475) 0x55a417 LEA 0x8(,%R14,8),%R13 |
(2475) 0x55a41f MOV (%R10,%R14,8),%RAX |
(2475) 0x55a423 ADD %R13,%R10 |
(2475) 0x55a426 MOV %R10,-0xa8(%RBP) |
(2475) 0x55a42d MOV (%R10),%R10 |
(2475) 0x55a430 CMP %R10,%RAX |
(2475) 0x55a433 JGE 55a481 |
(2475) 0x55a435 MOV %RDX,-0xd8(%RBP) |
(2475) 0x55a43c NOPL (%RAX) |
(2477) 0x55a440 MOV -0x60(%RBP),%R9 |
(2477) 0x55a444 MOV (%R9,%RAX,8),%RCX |
(2477) 0x55a448 LEA (%R12,%RCX,1),%RDX |
(2477) 0x55a44c LEA (%R8,%RDX,8),%R9 |
(2477) 0x55a450 MOV -0x68(%RBP),%RDX |
(2477) 0x55a454 MOV (%R9),%R15 |
(2477) 0x55a457 VMULSD (%RDX,%RAX,8),%XMM2,%XMM1 |
(2477) 0x55a45c CMP %R15,-0x40(%RBP) |
(2477) 0x55a460 JG 55a620 |
(2477) 0x55a466 LEA (%R11,%R15,8),%RCX |
(2477) 0x55a46a INC %RAX |
(2477) 0x55a46d VADDSD (%RCX),%XMM1,%XMM4 |
(2477) 0x55a471 VMOVSD %XMM4,(%RCX) |
(2477) 0x55a475 CMP %R10,%RAX |
(2477) 0x55a478 JL 55a440 |
(2475) 0x55a47a MOV -0xd8(%RBP),%RDX |
(2475) 0x55a481 MOV -0xf0(%RBP),%RCX |
(2475) 0x55a488 MOV (%RCX,%R14,8),%RAX |
(2475) 0x55a48c ADD %R13,%RCX |
(2475) 0x55a48f MOV (%RCX),%R13 |
(2475) 0x55a492 MOV %RCX,%R15 |
(2475) 0x55a495 CMP %R13,%RAX |
(2475) 0x55a498 JGE 55a4d7 |
(2475) 0x55a49a NOPW (%RAX,%RAX,1) |
(2476) 0x55a4a0 MOV -0x70(%RBP),%R14 |
(2476) 0x55a4a4 MOV -0x78(%RBP),%R9 |
(2476) 0x55a4a8 MOV (%R14,%RAX,8),%RCX |
(2476) 0x55a4ac VMULSD (%R9,%RAX,8),%XMM2,%XMM5 |
(2476) 0x55a4b2 LEA (%R8,%RCX,8),%R10 |
(2476) 0x55a4b6 MOV (%R10),%R14 |
(2476) 0x55a4b9 CMP %R14,-0x48(%RBP) |
(2476) 0x55a4bd JG 55a5f0 |
(2476) 0x55a4c3 LEA (%RBX,%R14,8),%RCX |
(2476) 0x55a4c7 INC %RAX |
(2476) 0x55a4ca VADDSD (%RCX),%XMM5,%XMM6 |
(2476) 0x55a4ce VMOVSD %XMM6,(%RCX) |
(2476) 0x55a4d2 CMP %R13,%RAX |
(2476) 0x55a4d5 JL 55a4a0 |
(2475) 0x55a4d7 MOV -0xe0(%RBP),%RAX |
(2475) 0x55a4de MOV -0xa0(%RBP),%R15 |
(2475) 0x55a4e5 INC %RDI |
(2475) 0x55a4e8 CMP %RDI,0x8(%RAX,%R15,8) |
(2475) 0x55a4ed JG 55a3f8 |
0x55a4f3 MOV -0x48(%RBP),%R12 |
0x55a4f7 JMP 55a282 |
(2481) 0x55a500 MOV -0x38(%RBP),%R10 |
(2481) 0x55a504 MOV %RDX,(%RSI) |
(2481) 0x55a507 INC %RAX |
(2481) 0x55a50a VMOVSD %XMM8,(%RBX,%RDX,8) |
(2481) 0x55a50f MOV %RCX,(%R10,%RDX,8) |
(2481) 0x55a513 INC %RDX |
(2481) 0x55a516 MOV (%R14),%R10 |
(2481) 0x55a519 CMP %RAX,%R10 |
(2481) 0x55a51c JG 55a300 |
(2479) 0x55a522 CMPQ $0,-0xb8(%RBP) |
(2479) 0x55a52a JE 55a33d |
(2479) 0x55a530 MOV -0xf8(%RBP),%R14 |
(2479) 0x55a537 MOV (%R14,%RDI,8),%RAX |
(2479) 0x55a53b LEA (%R14,%R9,1),%R14 |
(2479) 0x55a53f MOV (%R14),%R10 |
(2479) 0x55a542 CMP %R10,%RAX |
(2479) 0x55a545 JGE 55a33d |
(2479) 0x55a54b MOV -0xa8(%RBP),%RSI |
(2479) 0x55a552 NOPW (%RAX,%RAX,1) |
(2480) 0x55a558 MOV -0x90(%RBP),%RDI |
(2480) 0x55a55f MOV -0x88(%RBP),%R15 |
(2480) 0x55a566 MOV (%RDI,%RAX,8),%R9 |
(2480) 0x55a56a MOV -0x58(%RBP),%RDI |
(2480) 0x55a56e MOV (%R15,%R9,8),%RCX |
(2480) 0x55a572 MOV -0x98(%RBP),%R15 |
(2480) 0x55a579 VMULSD (%R15,%RAX,8),%XMM7,%XMM10 |
(2480) 0x55a57f ADD %RCX,%RDI |
(2480) 0x55a582 LEA (%R8,%RDI,8),%RDI |
(2480) 0x55a586 MOV (%RDI),%R9 |
(2480) 0x55a589 CMP %R9,-0x40(%RBP) |
(2480) 0x55a58d JG 55a5b8 |
(2480) 0x55a58f MOV -0x50(%RBP),%RCX |
(2480) 0x55a593 INC %RAX |
(2480) 0x55a596 LEA (%RCX,%R9,8),%RDI |
(2480) 0x55a59a VADDSD (%RDI),%XMM10,%XMM11 |
(2480) 0x55a59e VMOVSD %XMM11,(%RDI) |
(2480) 0x55a5a2 CMP %R10,%RAX |
(2480) 0x55a5a5 JL 55a558 |
(2479) 0x55a5a7 MOV %RSI,-0xa8(%RBP) |
(2479) 0x55a5ae JMP 55a33d |
(2480) 0x55a5b8 MOV -0x50(%RBP),%R10 |
(2480) 0x55a5bc MOV -0x80(%RBP),%R9 |
(2480) 0x55a5c0 MOV %RSI,(%RDI) |
(2480) 0x55a5c3 INC %RAX |
(2480) 0x55a5c6 VMOVSD %XMM10,(%R10,%RSI,8) |
(2480) 0x55a5cc MOV %RCX,(%R9,%RSI,8) |
(2480) 0x55a5d0 INC %RSI |
(2480) 0x55a5d3 MOV (%R14),%R10 |
(2480) 0x55a5d6 CMP %RAX,%R10 |
(2480) 0x55a5d9 JG 55a558 |
(2479) 0x55a5df MOV %RSI,-0xa8(%RBP) |
(2479) 0x55a5e6 JMP 55a33d |
(2476) 0x55a5f0 MOV -0x38(%RBP),%R13 |
(2476) 0x55a5f4 MOV %RDX,(%R10) |
(2476) 0x55a5f7 INC %RAX |
(2476) 0x55a5fa VMOVSD %XMM5,(%RBX,%RDX,8) |
(2476) 0x55a5ff MOV %RCX,(%R13,%RDX,8) |
(2476) 0x55a604 INC %RDX |
(2476) 0x55a607 MOV (%R15),%R13 |
(2476) 0x55a60a CMP %RAX,%R13 |
(2476) 0x55a60d JG 55a4a0 |
(2475) 0x55a613 JMP 55a4d7 |
(2477) 0x55a620 MOV -0x80(%RBP),%R10 |
(2477) 0x55a624 MOV %RSI,(%R9) |
(2477) 0x55a627 INC %RAX |
(2477) 0x55a62a VMOVSD %XMM1,(%R11,%RSI,8) |
(2477) 0x55a630 MOV -0xa8(%RBP),%R9 |
(2477) 0x55a637 MOV %RCX,(%R10,%RSI,8) |
(2477) 0x55a63b INC %RSI |
(2477) 0x55a63e MOV (%R9),%R10 |
(2477) 0x55a641 CMP %R10,%RAX |
(2477) 0x55a644 JL 55a440 |
(2475) 0x55a64a JMP 55a47a |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_mv/par_csr_matop.c: 865 - 989 |
-------------------------------------------------------------------------------- |
865: for (i1 = ns; i1 < ne; i1++) |
[...] |
874: if ( allsquare ) |
[...] |
886: if (num_cols_offd_A) |
887: { |
888: for (jj2 = A_offd_i[i1]; jj2 < A_offd_i[i1+1]; jj2++) |
889: { |
890: i2 = A_offd_j[jj2]; |
891: a_entry = A_offd_data[jj2]; |
[...] |
897: for (jj3 = B_ext_offd_i[i2]; jj3 < B_ext_offd_i[i2+1]; jj3++) |
898: { |
899: i3 = num_cols_diag_B+B_ext_offd_j[jj3]; |
[...] |
907: if (B_marker[i3] < jj_row_begin_offd) |
908: { |
909: B_marker[i3] = jj_count_offd; |
910: C_offd_data[jj_count_offd] = a_entry*B_ext_offd_data[jj3]; |
911: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
912: jj_count_offd++; |
913: } |
914: else |
915: C_offd_data[B_marker[i3]] += a_entry*B_ext_offd_data[jj3]; |
916: } |
917: for (jj3 = B_ext_diag_i[i2]; jj3 < B_ext_diag_i[i2+1]; jj3++) |
918: { |
919: i3 = B_ext_diag_j[jj3]; |
920: if (B_marker[i3] < jj_row_begin_diag) |
921: { |
922: B_marker[i3] = jj_count_diag; |
923: C_diag_data[jj_count_diag] = a_entry*B_ext_diag_data[jj3]; |
924: C_diag_j[jj_count_diag] = i3; |
925: jj_count_diag++; |
926: } |
927: else |
928: C_diag_data[B_marker[i3]] += a_entry*B_ext_diag_data[jj3]; |
[...] |
937: for (jj2 = A_diag_i[i1]; jj2 < A_diag_i[i1+1]; jj2++) |
938: { |
939: i2 = A_diag_j[jj2]; |
940: a_entry = A_diag_data[jj2]; |
[...] |
946: for (jj3 = B_diag_i[i2]; jj3 < B_diag_i[i2+1]; jj3++) |
947: { |
948: i3 = B_diag_j[jj3]; |
[...] |
956: if (B_marker[i3] < jj_row_begin_diag) |
957: { |
958: B_marker[i3] = jj_count_diag; |
959: C_diag_data[jj_count_diag] = a_entry*B_diag_data[jj3]; |
960: C_diag_j[jj_count_diag] = i3; |
961: jj_count_diag++; |
962: } |
963: else |
964: { |
965: C_diag_data[B_marker[i3]] += a_entry*B_diag_data[jj3]; |
966: } |
967: } |
968: if (num_cols_offd_B) |
969: { |
970: for (jj3 = B_offd_i[i2]; jj3 < B_offd_i[i2+1]; jj3++) |
971: { |
972: i3 = num_cols_diag_B+map_B_to_C[B_offd_j[jj3]]; |
[...] |
980: if (B_marker[i3] < jj_row_begin_offd) |
981: { |
982: B_marker[i3] = jj_count_offd; |
983: C_offd_data[jj_count_offd] = a_entry*B_offd_data[jj3]; |
984: C_offd_j[jj_count_offd] = i3-num_cols_diag_B; |
985: jj_count_offd++; |
986: } |
987: else |
988: { |
989: C_offd_data[B_marker[i3]] += a_entry*B_offd_data[jj3]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | P2, P3, |
| Function | hypre_ParMatmul._omp_fn.3 |
| Source | par_csr_matop.c:865-989 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 10.00 |
| CQA cycles if no scalar integer | 10.00 |
| CQA cycles if FP arith vectorized | 10.00 |
| CQA cycles if fully vectorized | 1.25 |
| Front-end cycles | 9.75 |
| DIV/SQRT cycles | 3.00 |
| P0 cycles | 3.00 |
| P1 cycles | 10.00 |
| P2 cycles | 10.00 |
| P3 cycles | 5.00 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 5.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 10.15 |
| Stall cycles (UFS) | 0.43 |
| Nb insns | 35.00 |
| Nb uops | 37.00 |
| Nb loads | 20.00 |
| Nb stores | 5.00 |
| Nb stack references | 13.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 40.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.03 |
| Bottlenecks | P2, P3, |
| Function | hypre_ParMatmul._omp_fn.3 |
| Source | par_csr_matop.c:865-989 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 10.00 |
| CQA cycles if no scalar integer | 10.00 |
| CQA cycles if FP arith vectorized | 10.00 |
| CQA cycles if fully vectorized | 1.25 |
| Front-end cycles | 9.75 |
| DIV/SQRT cycles | 3.00 |
| P0 cycles | 3.00 |
| P1 cycles | 10.00 |
| P2 cycles | 10.00 |
| P3 cycles | 5.00 |
| P4 cycles | 3.00 |
| P5 cycles | 3.00 |
| P6 cycles | 5.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 10.15 |
| Stall cycles (UFS) | 0.43 |
| Nb insns | 35.00 |
| Nb uops | 37.00 |
| Nb loads | 20.00 |
| Nb stores | 5.00 |
| Nb stack references | 13.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 40.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | hypre_ParMatmul._omp_fn.3 |
| Source file and lines | par_csr_matop.c:865-989 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 37 |
| loop length | 198 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 13 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 10.00 | 10.00 | 5.00 | 3.00 | 3.00 | 5.00 |
| cycles | 3.00 | 3.00 | 10.00 | 10.00 | 5.00 | 3.00 | 3.00 | 5.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 10.15 |
| Stall cycles | 0.43 |
| LM full (events) | 1.74 |
| Front-end | 9.75 |
| Dispatch | 10.00 |
| Overall L1 | 10.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPQ $0,-0x118(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JNE 55a3c5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xb0(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0xa0(%RBP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R11,%R14,8),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %RDI,0x8(%R11,%R14,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 55a365 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x128(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x130(%RBP),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RSI,-0xa8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDI,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0xa8(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INCQ -0xa0(%RBP) | 3 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
| MOV -0xa0(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R12,-0x120(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 55a64f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0,-0x110(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RSI,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JE 55a26d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xe0(%RBP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R15,%RAX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP 0x8(%R15,%RAX,8),%R14 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JGE 55a282 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R12,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JMP 55a282 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_ParMatmul._omp_fn.3 |
| Source file and lines | par_csr_matop.c:865-989 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 37 |
| loop length | 198 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 13 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.00 | 3.00 | 10.00 | 10.00 | 5.00 | 3.00 | 3.00 | 5.00 |
| cycles | 3.00 | 3.00 | 10.00 | 10.00 | 5.00 | 3.00 | 3.00 | 5.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 10.15 |
| Stall cycles | 0.43 |
| LM full (events) | 1.74 |
| Front-end | 9.75 |
| Dispatch | 10.00 |
| Overall L1 | 10.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| CMPQ $0,-0x118(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV -0x40(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R12,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JNE 55a3c5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xb0(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0xa0(%RBP),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R11,%R14,8),%RDI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %RDI,0x8(%R11,%R14,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 55a365 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0x128(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x130(%RBP),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RSI,-0xa8(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDI,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0xa8(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| INCQ -0xa0(%RBP) | 3 | 0.25 | 0.25 | 0.83 | 0.83 | 1 | 0.25 | 0.25 | 0.33 | 5 | 1 |
| MOV -0xa0(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP %R12,-0x120(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JE 55a64f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0,-0x110(%RBP) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| MOV %RSI,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JE 55a26d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV -0xe0(%RBP),%R15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0xa0(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R15,%RAX,8),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CMP 0x8(%R15,%RAX,8),%R14 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JGE 55a282 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R12,-0x48(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x50(%RBP),%R11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R14,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x58(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x48(%RBP),%R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JMP 55a282 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
