| Loop Id: 4006 | Module: exec | Source: csr_matvec.c:248-263 [...] | Coverage: 1.22% |
|---|
| Loop Id: 4006 | Module: exec | Source: csr_matvec.c:248-263 [...] | Coverage: 1.22% |
|---|
0x4e9ea0 MOV 0x30(%RBP),%RAX |
0x4e9ea4 VMOVSD %XMM0,(%RAX,%R10,8) |
0x4e9eaa CMP -0x30(%RBP),%R12 |
0x4e9eae LEA 0x1(%R12),%R12 |
0x4e9eb3 JE 4eace0 |
0x4e9eb9 LEA (%RSI,%R12,1),%R10 |
0x4e9ebd MOV (%R14,%R10,8),%R8 |
0x4e9ec1 MOV 0x8(%R14,%R10,8),%RAX |
0x4e9ec6 VXORPD %XMM0,%XMM0,%XMM0 |
0x4e9eca MOV %RAX,%R13 |
0x4e9ecd SUB %R8,%R13 |
0x4e9ed0 JLE 4e9ea0 |
0x4e9ed2 MOV %R13,%RDX |
0x4e9ed5 AND $-0x4,%RDX |
0x4e9ed9 JE 4e9f40 |
0x4e9edb LEA -0x1(%RDX),%RCX |
0x4e9edf LEA (%R15,%R8,8),%RDI |
0x4e9ee3 LEA (%R11,%R8,8),%RBX |
0x4e9ee7 VXORPD %XMM0,%XMM0,%XMM0 |
0x4e9eeb XOR %ESI,%ESI |
0x4e9eed NOPL (%RAX) |
(4008) 0x4e9ef0 VMOVUPD (%RBX,%RSI,8),%YMM1 |
(4008) 0x4e9ef5 KXNORW %K0,%K0,%K1 |
(4008) 0x4e9ef9 VXORPD %XMM2,%XMM2,%XMM2 |
(4008) 0x4e9efd VGATHERQPD (%R9,%YMM1,8),%YMM2{%K1} |
(4008) 0x4e9f04 VFMADD231PD (%RDI,%RSI,8),%YMM2,%YMM0 |
(4008) 0x4e9f0a ADD $0x4,%RSI |
(4008) 0x4e9f0e CMP %RCX,%RSI |
(4008) 0x4e9f11 JBE 4e9ef0 |
0x4e9f13 VEXTRACTF128 $0x1,%YMM0,%XMM1 |
0x4e9f19 VADDPD %XMM1,%XMM0,%XMM0 |
0x4e9f1d VPERMILPD $0x1,%XMM0,%XMM1 |
0x4e9f23 VADDSD %XMM1,%XMM0,%XMM0 |
0x4e9f27 CMP %RDX,%R13 |
0x4e9f2a MOV -0x38(%RBP),%RSI |
0x4e9f2e JE 4e9ea0 |
0x4e9f34 JMP 4e9f46 |
0x4e9f40 VXORPD %XMM0,%XMM0,%XMM0 |
0x4e9f44 XOR %EDX,%EDX |
0x4e9f46 ADD %R8,%RDX |
0x4e9f49 NOPL (%RAX) |
(4007) 0x4e9f50 MOV (%R11,%RDX,8),%RCX |
(4007) 0x4e9f54 VMOVSD (%R9,%RCX,8),%XMM1 |
(4007) 0x4e9f5a VFMADD231SD (%R15,%RDX,8),%XMM1,%XMM0 |
(4007) 0x4e9f60 INC %RDX |
(4007) 0x4e9f63 CMP %RDX,%RAX |
(4007) 0x4e9f66 JNE 4e9f50 |
0x4e9f68 JMP 4e9ea0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 248 - 263 |
-------------------------------------------------------------------------------- |
248: hypre_assert(iBegin <= iEnd); |
[...] |
256: for (i = iBegin; i < iEnd; i++) |
257: { |
258: tempx = 0.0; |
259: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
260: { |
261: tempx += A_data[jj] * x_data[A_j[jj]]; |
262: } |
263: y_data[i] = tempx; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_CSRMatrixMatvecOutOfPlac[...] | csr_matvec.c:243 | exec |
| ○ | hypre_ParCSRMatrixMatvecOutOfP[...] | par_csr_matvec.c:216 | exec |
| ○ | hypre_PCGSolve | pcg.c:496 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.98 |
| CQA speedup if FP arith vectorized | 1.88 |
| CQA speedup if fully vectorized | 7.51 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.65 |
| Bottlenecks | |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-263 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.69 |
| CQA cycles if no scalar integer | 2.88 |
| CQA cycles if FP arith vectorized | 3.02 |
| CQA cycles if fully vectorized | 0.76 |
| Front-end cycles | 5.69 |
| DIV/SQRT cycles | 3.25 |
| P0 cycles | 3.25 |
| P1 cycles | 2.25 |
| P2 cycles | 2.25 |
| P3 cycles | 1.00 |
| P4 cycles | 3.25 |
| P5 cycles | 3.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 8.05 |
| Stall cycles (UFS) | 2.03 |
| Nb insns | 23.00 |
| Nb uops | 22.75 |
| Nb loads | 4.50 |
| Nb stores | 1.00 |
| Nb stack references | 2.50 |
| FLOP/cycle | 0.26 |
| Nb FLOP add-sub | 1.50 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.85 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 36.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.50 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 4.50 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 43.66 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 27.78 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 59.29 |
| Vector-efficiency ratio all | 17.96 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 15.97 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 19.91 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.83 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.38 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-263 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.75 |
| CQA cycles if no scalar integer | 1.50 |
| CQA cycles if FP arith vectorized | 2.75 |
| CQA cycles if fully vectorized | 0.34 |
| Front-end cycles | 2.75 |
| DIV/SQRT cycles | 1.25 |
| P0 cycles | 1.25 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.25 |
| P5 cycles | 1.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 2.87 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 12.00 |
| Nb uops | 11.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 14.55 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 32.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 33.33 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 16.67 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.00 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-263 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.00 |
| CQA cycles if no scalar integer | 2.50 |
| CQA cycles if FP arith vectorized | 5.00 |
| CQA cycles if fully vectorized | 0.63 |
| Front-end cycles | 5.00 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 2.50 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 1.00 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 5.12 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 20.00 |
| Nb uops | 20.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 32.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 5.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 33.33 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 16.67 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.13 |
| CQA speedup if FP arith vectorized | 3.41 |
| CQA speedup if fully vectorized | 7.31 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.60 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-263 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 3.75 |
| CQA cycles if FP arith vectorized | 2.34 |
| CQA cycles if fully vectorized | 1.09 |
| Front-end cycles | 8.00 |
| DIV/SQRT cycles | 5.00 |
| P0 cycles | 5.00 |
| P1 cycles | 2.50 |
| P2 cycles | 2.50 |
| P3 cycles | 1.00 |
| P4 cycles | 5.00 |
| P5 cycles | 5.00 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 12.11 |
| Stall cycles (UFS) | 3.56 |
| Nb insns | 32.00 |
| Nb uops | 32.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.38 |
| Nb FLOP add-sub | 3.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 40.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 7.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 45.45 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 57.14 |
| Vector-efficiency ratio all | 18.18 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 16.67 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 19.64 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.87 |
| CQA speedup if FP arith vectorized | 3.50 |
| CQA speedup if fully vectorized | 7.23 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.65 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-263 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.00 |
| CQA cycles if no scalar integer | 3.75 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 0.97 |
| Front-end cycles | 7.00 |
| DIV/SQRT cycles | 4.25 |
| P0 cycles | 4.25 |
| P1 cycles | 2.50 |
| P2 cycles | 2.50 |
| P3 cycles | 1.00 |
| P4 cycles | 4.25 |
| P5 cycles | 4.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 12.10 |
| Stall cycles (UFS) | 4.55 |
| Nb insns | 28.00 |
| Nb uops | 28.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.43 |
| Nb FLOP add-sub | 3.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 6.86 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 40.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 4.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 62.50 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 80.00 |
| Vector-efficiency ratio all | 20.31 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 18.75 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 22.50 |
| Path / |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-263 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 22.75 |
| loop length | 93.25 |
| used x86 registers | 11.25 |
| used mmx registers | 0 |
| used xmm registers | 1.50 |
| used ymm registers | 0.50 |
| used zmm registers | 0 |
| nb stack references | 2.50 |
| micro-operation queue | 5.69 cycles |
| front end | 5.69 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.25 | 3.25 | 2.25 | 2.25 | 1.00 | 3.25 | 3.25 | 1.00 |
| cycles | 3.25 | 3.25 | 2.25 | 2.25 | 1.00 | 3.25 | 3.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 8.05 |
| Stall cycles | 2.03 |
| ROB full (events) | 2.48 |
| Front-end | 5.69 |
| Dispatch | 3.44 |
| Data deps. | 0.00 |
| Overall L1 | 5.69 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 64% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 43% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 27% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 59% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 20% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 17% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 15% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 19% |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-263 |
| Module | exec |
| nb instructions | 12 |
| nb uops | 11 |
| loop length | 50 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 2.75 cycles |
| front end | 2.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.25 | 1.25 | 2.00 | 2.00 | 1.00 | 1.25 | 1.25 | 1.00 |
| cycles | 1.25 | 1.25 | 2.00 | 2.00 | 1.00 | 1.25 | 1.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 2.87 |
| Stall cycles | 0.00 |
| Front-end | 2.75 |
| Dispatch | 2.00 |
| Data deps. | 0.00 |
| Overall L1 | 2.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 33% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 18% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 16% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RSI,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R14,%R10,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R8,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-263 |
| Module | exec |
| nb instructions | 20 |
| nb uops | 20 |
| loop length | 80 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 5.00 cycles |
| front end | 5.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 2.00 | 2.00 | 1.00 | 2.50 | 2.50 | 1.00 |
| cycles | 2.50 | 2.50 | 2.00 | 2.00 | 1.00 | 2.50 | 2.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 5.12 |
| Stall cycles | 0.00 |
| Front-end | 5.00 |
| Dispatch | 2.50 |
| Data deps. | 0.00 |
| Overall L1 | 5.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 66% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 33% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 20% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 16% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RSI,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R14,%R10,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R8,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4e9f40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| ADD %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4e9ea0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-263 |
| Module | exec |
| nb instructions | 32 |
| nb uops | 32 |
| loop length | 130 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 1 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 8.00 cycles |
| front end | 8.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 5.00 | 5.00 | 2.50 | 2.50 | 1.00 | 5.00 | 5.00 | 1.00 |
| cycles | 5.00 | 5.00 | 2.50 | 2.50 | 1.00 | 5.00 | 5.00 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 12.11 |
| Stall cycles | 3.56 |
| ROB full (events) | 4.45 |
| Front-end | 8.00 |
| Dispatch | 5.00 |
| Data deps. | 0.00 |
| Overall L1 | 8.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 71% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 45% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 57% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 21% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 18% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 16% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 19% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RSI,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R14,%R10,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R8,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4e9f40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R15,%R8,8),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R11,%R8,8),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPERMILPD $0x1,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDX,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 4e9f46 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| ADD %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4e9ea0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-263 |
| Module | exec |
| nb instructions | 28 |
| nb uops | 28 |
| loop length | 113 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 1 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 7.00 cycles |
| front end | 7.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.25 | 4.25 | 2.50 | 2.50 | 1.00 | 4.25 | 4.25 | 1.00 |
| cycles | 4.25 | 4.25 | 2.50 | 2.50 | 1.00 | 4.25 | 4.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 12.10 |
| Stall cycles | 4.55 |
| ROB full (events) | 5.46 |
| Front-end | 7.00 |
| Dispatch | 4.25 |
| Data deps. | 0.00 |
| Overall L1 | 7.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 71% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 62% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 80% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 21% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 20% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 22% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RSI,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R14,%R10,8),%R8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %RAX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R8,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R13,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4e9f40 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RDX),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R15,%R8,8),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R11,%R8,8),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VEXTRACTF128 $0x1,%YMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPERMILPD $0x1,%XMM0,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDX,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV -0x38(%RBP),%RSI | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JE 4e9ea0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
