| Function: hypre_SeqVectorInnerProd._omp_fn.0 | Module: exec | Source: vector.c:483-486 | Coverage: 0.56% |
|---|
| Function: hypre_SeqVectorInnerProd._omp_fn.0 | Module: exec | Source: vector.c:483-486 | Coverage: 0.56% |
|---|
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/vector.c: 483 - 486 |
-------------------------------------------------------------------------------- |
483: #pragma omp parallel for private(i) reduction(+:result) HYPRE_SMP_SCHEDULE |
484: #endif |
485: for (i = 0; i < size; i++) |
486: result += hypre_conj(y_data[i]) * x_data[i]; |
0x5a8860 PUSH %RBP |
0x5a8861 MOV %RSP,%RBP |
0x5a8864 PUSH %R14 |
0x5a8866 PUSH %R13 |
0x5a8868 PUSH %R12 |
0x5a886a PUSH %RBX |
0x5a886b MOV %RDI,%RBX |
0x5a886e AND $-0x40,%RSP |
0x5a8872 MOV 0x8(%RDI),%R13 |
0x5a8876 MOV (%RDI),%R14 |
0x5a8879 CALL 40f0b0 <omp_get_num_threads@plt> |
0x5a887e MOVSXD %EAX,%R12 |
0x5a8881 CALL 40f1f0 <omp_get_thread_num@plt> |
0x5a8886 MOVSXD %EAX,%RCX |
0x5a8889 MOV 0x10(%RBX),%RAX |
0x5a888d CQTO |
0x5a888f IDIV %R12 |
0x5a8892 CMP %RDX,%RCX |
0x5a8895 JL 5a8b28 |
0x5a889b IMUL %RAX,%RCX |
0x5a889f VXORPD %XMM15,%XMM15,%XMM15 |
0x5a88a4 ADD %RCX,%RDX |
0x5a88a7 LEA (%RAX,%RDX,1),%R9 |
0x5a88ab CMP %R9,%RDX |
0x5a88ae JGE 5a8af2 |
0x5a88b4 LEA -0x1(%RAX),%RSI |
0x5a88b8 MOV %RDX,%R10 |
0x5a88bb CMP $0x6,%RSI |
0x5a88bf JBE 5a8b38 |
0x5a88c5 MOV %RAX,%R11 |
0x5a88c8 LEA (,%RDX,8),%R12 |
0x5a88d0 VXORPD %XMM8,%XMM8,%XMM8 |
0x5a88d5 XOR %ECX,%ECX |
0x5a88d7 SHR $0x3,%R11 |
0x5a88db LEA (%R13,%R12,1),%R8 |
0x5a88e0 ADD %R14,%R12 |
0x5a88e3 SAL $0x6,%R11 |
0x5a88e7 LEA -0x40(%R11),%RSI |
0x5a88eb SHR $0x6,%RSI |
0x5a88ef INC %RSI |
0x5a88f2 AND $0x7,%ESI |
0x5a88f5 JE 5a89aa |
0x5a88fb CMP $0x1,%RSI |
0x5a88ff JE 5a898f |
0x5a8905 CMP $0x2,%RSI |
0x5a8909 JE 5a897d |
0x5a890b CMP $0x3,%RSI |
0x5a890f JE 5a896b |
0x5a8911 CMP $0x4,%RSI |
0x5a8915 JE 5a8959 |
0x5a8917 CMP $0x5,%RSI |
0x5a891b JE 5a8947 |
0x5a891d CMP $0x6,%RSI |
0x5a8921 JE 5a8935 |
0x5a8923 VMOVUPD (%R8),%ZMM2 |
0x5a8929 MOV $0x40,%ECX |
0x5a892e VFMADD231PD (%R12),%ZMM2,%ZMM8 |
0x5a8935 VMOVUPD (%R8,%RCX,1),%ZMM1 |
0x5a893c VFMADD231PD (%R12,%RCX,1),%ZMM1,%ZMM8 |
0x5a8943 ADD $0x40,%RCX |
0x5a8947 VMOVUPD (%R8,%RCX,1),%ZMM6 |
0x5a894e VFMADD231PD (%R12,%RCX,1),%ZMM6,%ZMM8 |
0x5a8955 ADD $0x40,%RCX |
0x5a8959 VMOVUPD (%R8,%RCX,1),%ZMM7 |
0x5a8960 VFMADD231PD (%R12,%RCX,1),%ZMM7,%ZMM8 |
0x5a8967 ADD $0x40,%RCX |
0x5a896b VMOVUPD (%R8,%RCX,1),%ZMM5 |
0x5a8972 VFMADD231PD (%R12,%RCX,1),%ZMM5,%ZMM8 |
0x5a8979 ADD $0x40,%RCX |
0x5a897d VMOVUPD (%R8,%RCX,1),%ZMM3 |
0x5a8984 VFMADD231PD (%R12,%RCX,1),%ZMM3,%ZMM8 |
0x5a898b ADD $0x40,%RCX |
0x5a898f VMOVUPD (%R8,%RCX,1),%ZMM4 |
0x5a8996 VFMADD231PD (%R12,%RCX,1),%ZMM4,%ZMM8 |
0x5a899d ADD $0x40,%RCX |
0x5a89a1 CMP %R11,%RCX |
0x5a89a4 JE 5a8a38 |
(3163) 0x5a89aa VMOVUPD (%R8,%RCX,1),%ZMM9 |
(3163) 0x5a89b1 VMOVUPD 0x40(%R8,%RCX,1),%ZMM10 |
(3163) 0x5a89b9 VMOVUPD 0x80(%R8,%RCX,1),%ZMM11 |
(3163) 0x5a89c1 VMOVUPD 0xc0(%R8,%RCX,1),%ZMM12 |
(3163) 0x5a89c9 VFMADD231PD (%R12,%RCX,1),%ZMM9,%ZMM8 |
(3163) 0x5a89d0 VMOVUPD 0x100(%R8,%RCX,1),%ZMM13 |
(3163) 0x5a89d8 VMOVUPD 0x140(%R8,%RCX,1),%ZMM14 |
(3163) 0x5a89e0 VMOVUPD 0x180(%R8,%RCX,1),%ZMM15 |
(3163) 0x5a89e8 VMOVUPD 0x1c0(%R8,%RCX,1),%ZMM0 |
(3163) 0x5a89f0 VFMADD231PD 0x40(%R12,%RCX,1),%ZMM10,%ZMM8 |
(3163) 0x5a89f8 VFMADD231PD 0x80(%R12,%RCX,1),%ZMM11,%ZMM8 |
(3163) 0x5a8a00 VFMADD231PD 0xc0(%R12,%RCX,1),%ZMM12,%ZMM8 |
(3163) 0x5a8a08 VFMADD231PD 0x100(%R12,%RCX,1),%ZMM13,%ZMM8 |
(3163) 0x5a8a10 VFMADD231PD 0x140(%R12,%RCX,1),%ZMM14,%ZMM8 |
(3163) 0x5a8a18 VFMADD231PD 0x180(%R12,%RCX,1),%ZMM15,%ZMM8 |
(3163) 0x5a8a20 VFMADD231PD 0x1c0(%R12,%RCX,1),%ZMM0,%ZMM8 |
(3163) 0x5a8a28 ADD $0x200,%RCX |
(3163) 0x5a8a2f CMP %R11,%RCX |
(3163) 0x5a8a32 JNE 5a89aa |
0x5a8a38 VEXTRACTF64X4 $0x1,%ZMM8,%YMM6 |
0x5a8a3f MOV %RAX,%RDI |
0x5a8a42 VADDPD %YMM8,%YMM6,%YMM1 |
0x5a8a47 AND $-0x8,%RDI |
0x5a8a4b VADDPD %YMM6,%YMM8,%YMM0 |
0x5a8a4f ADD %RDI,%RDX |
0x5a8a52 VEXTRACTF64X2 $0x1,%YMM1,%XMM2 |
0x5a8a59 VADDPD %XMM1,%XMM2,%XMM7 |
0x5a8a5d VUNPCKHPD %XMM7,%XMM7,%XMM5 |
0x5a8a61 VADDPD %XMM7,%XMM5,%XMM15 |
0x5a8a65 CMP %RAX,%RDI |
0x5a8a68 JE 5a8b20 |
0x5a8a6e SUB %RDI,%RAX |
0x5a8a71 LEA -0x1(%RAX),%R12 |
0x5a8a75 CMP $0x2,%R12 |
0x5a8a79 JBE 5a8aac |
0x5a8a7b ADD %R10,%RDI |
0x5a8a7e MOV %RAX,%R10 |
0x5a8a81 VMOVUPD (%R13,%RDI,8),%YMM8 |
0x5a8a88 AND $-0x4,%R10 |
0x5a8a8c ADD %R10,%RDX |
0x5a8a8f VFMADD231PD (%R14,%RDI,8),%YMM8,%YMM0 |
0x5a8a95 VEXTRACTF64X2 $0x1,%YMM0,%XMM3 |
0x5a8a9c VADDPD %XMM0,%XMM3,%XMM4 |
0x5a8aa0 VUNPCKHPD %XMM4,%XMM4,%XMM9 |
0x5a8aa4 VADDPD %XMM4,%XMM9,%XMM15 |
0x5a8aa8 TEST $0x3,%AL |
0x5a8aaa JE 5a8b20 |
0x5a8aac VMOVSD (%R13,%RDX,8),%XMM10 |
0x5a8ab3 LEA 0x1(%RDX),%RDI |
0x5a8ab7 LEA (,%RDX,8),%RAX |
0x5a8abf VFMADD231SD (%R14,%RDX,8),%XMM10,%XMM15 |
0x5a8ac5 CMP %RDI,%R9 |
0x5a8ac8 JLE 5a8b20 |
0x5a8aca VMOVSD 0x8(%R14,%RAX,1),%XMM11 |
0x5a8ad1 ADD $0x2,%RDX |
0x5a8ad5 VFMADD231SD 0x8(%R13,%RAX,1),%XMM11,%XMM15 |
0x5a8adc CMP %RDX,%R9 |
0x5a8adf JLE 5a8b20 |
0x5a8ae1 VMOVSD 0x10(%R13,%RAX,1),%XMM12 |
0x5a8ae8 VFMADD231SD 0x10(%R14,%RAX,1),%XMM12,%XMM15 |
0x5a8aef VZEROUPPER |
0x5a8af2 MOV 0x18(%RBX),%RAX |
0x5a8af6 LEA 0x18(%RBX),%R13 |
(3162) 0x5a8afa VMOVQ %RAX,%XMM13 |
(3162) 0x5a8aff VADDSD %XMM13,%XMM15,%XMM14 |
(3162) 0x5a8b04 VMOVQ %XMM14,%RBX |
(3162) 0x5a8b09 LOCK CMPXCHG %RBX,(%R13) |
(3162) 0x5a8b0f JNE 5a8afa |
0x5a8b11 LEA -0x20(%RBP),%RSP |
0x5a8b15 POP %RBX |
0x5a8b16 POP %R12 |
0x5a8b18 POP %R13 |
0x5a8b1a POP %R14 |
0x5a8b1c POP %RBP |
0x5a8b1d RET |
0x5a8b1e XCHG %AX,%AX |
0x5a8b20 VZEROUPPER |
0x5a8b23 JMP 5a8af2 |
0x5a8b25 NOPL (%RAX) |
0x5a8b28 INC %RAX |
0x5a8b2b XOR %EDX,%EDX |
0x5a8b2d JMP 5a889b |
0x5a8b32 NOPW (%RAX,%RAX,1) |
0x5a8b38 VXORPD %XMM0,%XMM0,%XMM0 |
0x5a8b3c XOR %EDI,%EDI |
0x5a8b3e JMP 5a8a6e |
0x5a8b43 NOPW %CS:(%RAX,%RAX,1) |
0x5a8b4e XCHG %AX,%AX |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Source file and lines | vector.c:483-486 |
| Module | exec |
| nb instructions | 141 |
| nb uops | 205 |
| loop length | 587 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 13 |
| used ymm registers | 4 |
| used zmm registers | 8 |
| nb stack references | 1 |
| micro-operation queue | 53.75 cycles |
| front end | 53.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 38.25 | 38.25 | 15.50 | 15.50 | 7.00 | 38.25 | 38.25 | 8.00 |
| cycles | 38.25 | 38.25 | 15.50 | 15.50 | 7.00 | 38.25 | 38.25 | 8.00 |
| Cycles executing div or sqrt instructions | 24.00-90.00 |
| FE+BE cycles | 40.37-90.47 |
| Stall cycles | 1.57-51.67 |
| ROB full (events) | 1.84-52.91 |
| Front-end | 53.75 |
| Dispatch | 38.25 |
| DIV/SQRT | 24.00-90.00 |
| Overall L1 | 53.75-90.00 |
| all | 8% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 77% |
| load | 72% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 72% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 75% |
| all | 49% |
| load | 72% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 85% |
| fma | 72% |
| div/sqrt | 0% |
| other | 25% |
| all | 13% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 13% |
| all | 54% |
| load | 71% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | 71% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 37% |
| load | 71% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 30% |
| fma | 71% |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV 0x8(%RDI),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RDI),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CALL 40f0b0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| MOVSXD %EAX,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CALL 40f1f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| MOVSXD %EAX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV 0x10(%RBX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| IDIV %R12 | 57 | 14.25 | 14.25 | 0 | 0 | 0 | 14.25 | 14.25 | 0 | 42-95 | 24-90 |
| CMP %RDX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JL 5a8b28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VXORPD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| ADD %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%RAX,%RDX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 5a8af2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RAX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RDX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| CMP $0x6,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JBE 5a8b38 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| LEA (,%RDX,8),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SHR $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA (%R13,%R12,1),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD %R14,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| SAL $0x6,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA -0x40(%R11),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| SHR $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x7,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a89aa | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a898f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a897d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x3,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a896b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8959 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x5,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8947 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x6,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8935 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVUPD (%R8),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| MOV $0x40,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231PD (%R12),%ZMM2,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R8,%RCX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM1,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM6,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM3,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R11,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8a38 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VEXTRACTF64X4 $0x1,%ZMM8,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VADDPD %YMM8,%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| AND $-0x8,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VADDPD %YMM6,%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| ADD %RDI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VEXTRACTF64X2 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM1,%XMM2,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM7,%XMM7,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDPD %XMM7,%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA -0x1(%RAX),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP $0x2,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JBE 5a8aac | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD %R10,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV %RAX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVUPD (%R13,%RDI,8),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| AND $-0x4,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD %R10,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231PD (%R14,%RDI,8),%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VEXTRACTF64X2 $0x1,%YMM0,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM0,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM4,%XMM4,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDPD %XMM4,%XMM9,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| TEST $0x3,%AL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%R13,%RDX,8),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA 0x1(%RDX),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (,%RDX,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VFMADD231SD (%R14,%RDX,8),%XMM10,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD 0x8(%R14,%RAX,1),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231SD 0x8(%R13,%RAX,1),%XMM11,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD 0x10(%R13,%RAX,1),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD231SD 0x10(%R14,%RAX,1),%XMM12,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| MOV 0x18(%RBX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA 0x18(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA -0x20(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JMP 5a8af2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 5a889b | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 5a8a6e | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| Source file and lines | vector.c:483-486 |
| Module | exec |
| nb instructions | 141 |
| nb uops | 205 |
| loop length | 587 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 13 |
| used ymm registers | 4 |
| used zmm registers | 8 |
| nb stack references | 1 |
| micro-operation queue | 53.75 cycles |
| front end | 53.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 38.25 | 38.25 | 15.50 | 15.50 | 7.00 | 38.25 | 38.25 | 8.00 |
| cycles | 38.25 | 38.25 | 15.50 | 15.50 | 7.00 | 38.25 | 38.25 | 8.00 |
| Cycles executing div or sqrt instructions | 24.00-90.00 |
| FE+BE cycles | 40.37-90.47 |
| Stall cycles | 1.57-51.67 |
| ROB full (events) | 1.84-52.91 |
| Front-end | 53.75 |
| Dispatch | 38.25 |
| DIV/SQRT | 24.00-90.00 |
| Overall L1 | 53.75-90.00 |
| all | 8% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 8% |
| all | 77% |
| load | 72% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 72% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 75% |
| all | 49% |
| load | 72% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 85% |
| fma | 72% |
| div/sqrt | 0% |
| other | 25% |
| all | 13% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 13% |
| all | 54% |
| load | 71% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | 71% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 37% |
| load | 71% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 30% |
| fma | 71% |
| div/sqrt | 12% |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| PUSH %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| PUSH %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDI,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x40,%RSP | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV 0x8(%RDI),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%RDI),%R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CALL 40f0b0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| MOVSXD %EAX,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CALL 40f1f0 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| MOVSXD %EAX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV 0x10(%RBX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| CQTO | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| IDIV %R12 | 57 | 14.25 | 14.25 | 0 | 0 | 0 | 14.25 | 14.25 | 0 | 42-95 | 24-90 |
| CMP %RDX,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JL 5a8b28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| IMUL %RAX,%RCX | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VXORPD %XMM15,%XMM15,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| ADD %RCX,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA (%RAX,%RDX,1),%R9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R9,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 5a8af2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RAX),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RDX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| CMP $0x6,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JBE 5a8b38 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %RAX,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| LEA (,%RDX,8),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %ECX,%ECX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SHR $0x3,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA (%R13,%R12,1),%R8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD %R14,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| SAL $0x6,%R11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA -0x40(%R11),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| SHR $0x6,%RSI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| AND $0x7,%ESI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a89aa | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x1,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a898f | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x2,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a897d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x3,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a896b | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8959 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x5,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8947 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x6,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8935 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVUPD (%R8),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| MOV $0x40,%ECX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231PD (%R12),%ZMM2,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R8,%RCX,1),%ZMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM1,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM6,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM7,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM3,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVUPD (%R8,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| VFMADD231PD (%R12,%RCX,1),%ZMM4,%ZMM8 | 1 | 0.50 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0 | 0 | 4 | 0.50 |
| ADD $0x40,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R11,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8a38 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VEXTRACTF64X4 $0x1,%ZMM8,%YMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| MOV %RAX,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VADDPD %YMM8,%YMM6,%YMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| AND $-0x8,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VADDPD %YMM6,%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| ADD %RDI,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VEXTRACTF64X2 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM1,%XMM2,%XMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM7,%XMM7,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDPD %XMM7,%XMM5,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| SUB %RDI,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| LEA -0x1(%RAX),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP $0x2,%R12 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JBE 5a8aac | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD %R10,%RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV %RAX,%R10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVUPD (%R13,%RDI,8),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5-6 | 0.50 |
| AND $-0x4,%R10 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD %R10,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231PD (%R14,%RDI,8),%YMM8,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VEXTRACTF64X2 $0x1,%YMM0,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM0,%XMM3,%XMM4 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM4,%XMM4,%XMM9 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDPD %XMM4,%XMM9,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| TEST $0x3,%AL | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD (%R13,%RDX,8),%XMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA 0x1(%RDX),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (,%RDX,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VFMADD231SD (%R14,%RDX,8),%XMM10,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD 0x8(%R14,%RAX,1),%XMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| ADD $0x2,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VFMADD231SD 0x8(%R13,%RAX,1),%XMM11,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RDX,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 5a8b20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| VMOVSD 0x10(%R13,%RAX,1),%XMM12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD231SD 0x10(%R14,%RAX,1),%XMM12,%XMM15 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| MOV 0x18(%RBX),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| LEA 0x18(%RBX),%R13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA -0x20(%RBP),%RSP | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| POP %RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R12 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %R14 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| POP %RBP | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 2 | 0.50 |
| RET | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 1 | 0.33 | 0 | 1 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JMP 5a8af2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| INC %RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 5a889b | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPW (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VXORPD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 5a8a6e | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼hypre_SeqVectorInnerProd._omp_fn.0– | 0.56 | 0.2 |
| ○Loop 3163 - vector.c:486-486 - exec | 0.56 | 0.2 |
| ○Loop 3162 - vector.c:483-483 - exec | 0 | 0 |
