| Loop Id: 3936 | Module: exec | Source: csr_matvec.c:485-615 [...] | Coverage: 0.59% |
|---|
| Loop Id: 3936 | Module: exec | Source: csr_matvec.c:485-615 [...] | Coverage: 0.59% |
|---|
0x4d3d80 LEA 0x1(%RDX),%RAX |
0x4d3d84 CMP %R8,%RDX |
0x4d3d87 MOV %RAX,%RDX |
0x4d3d8a JE 4d4290 |
0x4d3d90 MOV %R10,%RSI |
0x4d3d93 MOV -0x48(%RBP),%RAX |
0x4d3d97 MOV 0x8(%RAX,%RDX,8),%R10 |
0x4d3d9c MOV %R10,%R9 |
0x4d3d9f SUB %RSI,%R9 |
0x4d3da2 JLE 4d3d80 |
0x4d3da4 CMP $0x4,%R9 |
0x4d3da8 JB 4d3e3c |
0x4d3dae MOV %R9,%RDI |
0x4d3db1 SHR $0x2,%RDI |
0x4d3db5 LEA 0x18(,%RSI,8),%RAX |
0x4d3dbd NOPL (%RAX) |
(3938) 0x4d3dc0 VMOVSD (%R15,%RDX,8),%XMM0 |
(3938) 0x4d3dc6 VMOVSD -0x18(%R12,%RAX,1),%XMM1 |
(3938) 0x4d3dcd MOV -0x18(%R13,%RAX,1),%RCX |
(3938) 0x4d3dd2 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3938) 0x4d3dd8 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3938) 0x4d3ddd MOV -0x10(%R13,%RAX,1),%RCX |
(3938) 0x4d3de2 VMOVSD (%R15,%RDX,8),%XMM0 |
(3938) 0x4d3de8 VMOVSD -0x10(%R12,%RAX,1),%XMM1 |
(3938) 0x4d3def VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3938) 0x4d3df5 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3938) 0x4d3dfa MOV -0x8(%R13,%RAX,1),%RCX |
(3938) 0x4d3dff VMOVSD (%R15,%RDX,8),%XMM0 |
(3938) 0x4d3e05 VMOVSD -0x8(%R12,%RAX,1),%XMM1 |
(3938) 0x4d3e0c VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3938) 0x4d3e12 VMOVSD %XMM1,(%RBX,%RCX,8) |
(3938) 0x4d3e17 MOV (%R13,%RAX,1),%RCX |
(3938) 0x4d3e1c VMOVSD (%R15,%RDX,8),%XMM0 |
(3938) 0x4d3e22 VMOVSD (%R12,%RAX,1),%XMM1 |
(3938) 0x4d3e28 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 |
(3938) 0x4d3e2e VMOVSD %XMM1,(%RBX,%RCX,8) |
(3938) 0x4d3e33 ADD $0x20,%RAX |
(3938) 0x4d3e37 DEC %RDI |
(3938) 0x4d3e3a JNE 4d3dc0 |
0x4d3e3c MOV %R9,%RAX |
0x4d3e3f AND $-0x4,%RAX |
0x4d3e43 CMP %R9,%RAX |
0x4d3e46 JAE 4d3d80 |
0x4d3e4c ADD %RAX,%RSI |
0x4d3e4f NOP |
(3937) 0x4d3e50 MOV (%R13,%RSI,8),%RAX |
(3937) 0x4d3e55 VMOVSD (%R15,%RDX,8),%XMM0 |
(3937) 0x4d3e5b VMOVSD (%R12,%RSI,8),%XMM1 |
(3937) 0x4d3e61 VFMADD213SD (%RBX,%RAX,8),%XMM0,%XMM1 |
(3937) 0x4d3e67 VMOVSD %XMM1,(%RBX,%RAX,8) |
(3937) 0x4d3e6c INC %RSI |
(3937) 0x4d3e6f CMP %RSI,%R10 |
(3937) 0x4d3e72 JNE 4d3e50 |
0x4d3e74 JMP 4d3d80 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 485 - 615 |
-------------------------------------------------------------------------------- |
485: hypre_assert( num_vectors == hypre_VectorNumVectors(y) ); |
[...] |
608: for (i = 0; i < num_rows; i++) |
609: { |
610: if ( num_vectors==1 ) |
611: { |
612: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
613: { |
614: j = A_j[jj]; |
615: y_data[j] += A_data[jj] * x_data[i]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►97.67+ | hypre_ParCSRMatrixMatvecT | par_csr_matvec.c:432 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:435 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:545 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 | |
| ►2.33+ | hypre_ParCSRMatrixMatvecT | par_csr_matvec.c:432 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:435 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:424 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.64 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecT |
| Source | csr_matvec.c:485-615 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 5.75 |
| CQA cycles if FP arith vectorized | 5.75 |
| CQA cycles if fully vectorized | 0.72 |
| Front-end cycles | 5.75 |
| DIV/SQRT cycles | 3.50 |
| P0 cycles | 3.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 0.00 |
| P4 cycles | 3.50 |
| P5 cycles | 3.50 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 5.88 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | 2.00 |
| Nb stores | 0.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.78 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 16.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.64 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecT |
| Source | csr_matvec.c:485-615 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 5.75 |
| CQA cycles if FP arith vectorized | 5.75 |
| CQA cycles if fully vectorized | 0.72 |
| Front-end cycles | 5.75 |
| DIV/SQRT cycles | 3.50 |
| P0 cycles | 3.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 0.00 |
| P4 cycles | 3.50 |
| P5 cycles | 3.50 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 5.88 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 23.00 |
| Nb uops | 23.00 |
| Nb loads | 2.00 |
| Nb stores | 0.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 2.78 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 16.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | hypre_CSRMatrixMatvecT |
| Source file and lines | csr_matvec.c:485-615 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 23 |
| loop length | 89 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 5.75 cycles |
| front end | 5.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 3.50 | 1.00 | 1.00 | 0.00 | 3.50 | 3.50 | 0.00 |
| cycles | 3.50 | 3.50 | 1.00 | 1.00 | 0.00 | 3.50 | 3.50 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 5.88 |
| Stall cycles | 0.00 |
| Front-end | 5.75 |
| Dispatch | 3.50 |
| Overall L1 | 5.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA 0x1(%RDX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JE 4d4290 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%RAX,%RDX,8),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4d3d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JB 4d3e3c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R9,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA 0x18(,%RSI,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %R9,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R9,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JAE 4d3d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD %RAX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4d3d80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_CSRMatrixMatvecT |
| Source file and lines | csr_matvec.c:485-615 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 23 |
| loop length | 89 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 1 |
| micro-operation queue | 5.75 cycles |
| front end | 5.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 3.50 | 1.00 | 1.00 | 0.00 | 3.50 | 3.50 | 0.00 |
| cycles | 3.50 | 3.50 | 1.00 | 1.00 | 0.00 | 3.50 | 3.50 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 5.88 |
| Stall cycles | 0.00 |
| Front-end | 5.75 |
| Dispatch | 3.50 |
| Overall L1 | 5.75 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| LEA 0x1(%RDX),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R8,%RDX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV %RAX,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JE 4d4290 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R10,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV -0x48(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%RAX,%RDX,8),%R10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %R10,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %RSI,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4d3d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMP $0x4,%R9 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JB 4d3e3c | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R9,%RDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SHR $0x2,%RDI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 1 | 0.50 |
| LEA 0x18(,%RSI,8),%RAX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| MOV %R9,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMP %R9,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JAE 4d3d80 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| ADD %RAX,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4d3d80 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
