| Loop Id: 402 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
|---|
| Loop Id: 402 | Module: exec | Source: par_indepset.c:65-67 | Coverage: 0.01% |
|---|
0x431210 VZEROUPPER |
0x431213 CALL 4f6070 <hypre_Rand> |
0x431218 VMOVUPD %XMM0,-0x60(%RBP) [1] |
0x43121d CALL 4f6070 <hypre_Rand> |
0x431222 VMOVUPD %XMM0,-0x50(%RBP) [1] |
0x431227 CALL 4f6070 <hypre_Rand> |
0x43122c VMOVUPD %XMM0,-0x40(%RBP) [1] |
0x431231 CALL 4f6070 <hypre_Rand> |
0x431236 VMOVUPD -0x60(%RBP),%XMM1 [1] |
0x43123b VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 [1] |
0x431240 VMOVUPD -0x40(%RBP),%XMM2 [1] |
0x431245 VUNPCKLPD %XMM0,%XMM2,%XMM0 |
0x431249 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
0x43124f VADDPD -0x20(%RBX),%YMM0,%YMM0 [2] |
0x431254 VMOVUPD %YMM0,-0x20(%RBX) [2] |
0x431259 VZEROUPPER |
0x43125c CALL 4f6070 <hypre_Rand> |
0x431261 VMOVUPD %XMM0,-0x60(%RBP) [1] |
0x431266 CALL 4f6070 <hypre_Rand> |
0x43126b VMOVUPD %XMM0,-0x50(%RBP) [1] |
0x431270 CALL 4f6070 <hypre_Rand> |
0x431275 VMOVUPD %XMM0,-0x40(%RBP) [1] |
0x43127a CALL 4f6070 <hypre_Rand> |
0x43127f VMOVUPD -0x60(%RBP),%XMM1 [1] |
0x431284 VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 [1] |
0x431289 VMOVUPD -0x40(%RBP),%XMM2 [1] |
0x43128e VUNPCKLPD %XMM0,%XMM2,%XMM0 |
0x431292 VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 |
0x431298 VADDPD (%RBX),%YMM0,%YMM0 [2] |
0x43129c VMOVUPD %YMM0,(%RBX) [2] |
0x4312a0 ADD $0x40,%RBX |
0x4312a4 DEC %R14 |
0x4312a7 JNE 431210 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_indepset.c: 65 - 67 |
-------------------------------------------------------------------------------- |
65: for (i = 0; i < S_num_nodes; i++) |
66: { |
67: measure_array[i] += hypre_Rand(); |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_BoomerAMGCoarsenPMIS | par_coarsen.c:2084 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:601 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.22 |
| CQA speedup if fully vectorized | 4.47 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.39 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGIndepSetInit |
| Source | par_indepset.c:65-67 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 13.09 |
| CQA cycles if fully vectorized | 3.58 |
| Front-end cycles | 11.50 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 16.00 |
| P4 cycles | 6.00 |
| P5 cycles | 8.00 |
| P6 cycles | 8.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 16 |
| FE+BE cycles (UFS) | 16.16 |
| Stall cycles (UFS) | 7.62 |
| Nb insns | 33.00 |
| Nb uops | 46.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 160.00 |
| Stride 0 | 1.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 81.82 |
| Vectorization ratio load | 75.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 27.27 |
| Vector-efficiency ratio load | 28.13 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.22 |
| CQA speedup if fully vectorized | 4.47 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.39 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGIndepSetInit |
| Source | par_indepset.c:65-67 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 13.09 |
| CQA cycles if fully vectorized | 3.58 |
| Front-end cycles | 11.50 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 16.00 |
| P4 cycles | 6.00 |
| P5 cycles | 8.00 |
| P6 cycles | 8.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 16 |
| FE+BE cycles (UFS) | 16.16 |
| Stall cycles (UFS) | 7.62 |
| Nb insns | 33.00 |
| Nb uops | 46.00 |
| Nb loads | 8.00 |
| Nb stores | 8.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.50 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 160.00 |
| Stride 0 | 1.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 81.82 |
| Vectorization ratio load | 75.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 27.27 |
| Vector-efficiency ratio load | 28.13 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Path / |
| Function | hypre_BoomerAMGIndepSetInit |
| Source file and lines | par_indepset.c:65-67 |
| Module | exec |
| nb instructions | 33 |
| nb uops | 46 |
| loop length | 157 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 2 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 11.50 cycles |
| front end | 11.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 8.00 | 8.00 | 16.00 | 6.00 | 8.00 | 8.00 |
| cycles | 2.00 | 2.00 | 8.00 | 8.00 | 16.00 | 6.00 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 16.00 |
| FE+BE cycles | 16.16 |
| Stall cycles | 7.62 |
| RS full (events) | 15.32 |
| Front-end | 11.50 |
| Dispatch | 16.00 |
| Data deps. | 16.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 80% |
| load | 75% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 33% |
| all | 81% |
| load | 75% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 27% |
| load | 28% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 27% |
| load | 28% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD -0x60(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVUPD -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD -0x20(%RBX),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM0,-0x20(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD -0x60(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVUPD -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD (%RBX),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM0,(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x40,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 431210 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_BoomerAMGIndepSetInit |
| Source file and lines | par_indepset.c:65-67 |
| Module | exec |
| nb instructions | 33 |
| nb uops | 46 |
| loop length | 157 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 2 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 11.50 cycles |
| front end | 11.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 8.00 | 8.00 | 16.00 | 6.00 | 8.00 | 8.00 |
| cycles | 2.00 | 2.00 | 8.00 | 8.00 | 16.00 | 6.00 | 8.00 | 8.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 16.00 |
| FE+BE cycles | 16.16 |
| Stall cycles | 7.62 |
| RS full (events) | 15.32 |
| Front-end | 11.50 |
| Dispatch | 16.00 |
| Data deps. | 16.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 100% |
| all | 80% |
| load | 75% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 33% |
| all | 81% |
| load | 75% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 25% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 27% |
| load | 28% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| all | 27% |
| load | 28% |
| store | 31% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD -0x60(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVUPD -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD -0x20(%RBX),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM0,-0x20(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| VZEROUPPER | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x60(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x50(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD %XMM0,-0x40(%RBP) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CALL 4f6070 | 2 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 1 | 0.33 | 0 | 1 |
| VMOVUPD -0x60(%RBP),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD -0x50(%RBP),%XMM1,%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVUPD -0x40(%RBP),%XMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VUNPCKLPD %XMM0,%XMM2,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VINSERTF128 $0x1,%XMM0,%YMM1,%YMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD (%RBX),%YMM0,%YMM0 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %YMM0,(%RBX) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x40,%RBX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %R14 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 431210 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
