| Loop Id: 3988 | Module: exec | Source: csr_matvec.c:248-341 [...] | Coverage: 0.78% |
|---|
| Loop Id: 3988 | Module: exec | Source: csr_matvec.c:248-341 [...] | Coverage: 0.78% |
|---|
0x4ea240 MOV 0x30(%RBP),%RAX |
0x4ea244 VMOVSD %XMM0,(%RAX,%R10,8) |
0x4ea24a CMP -0x30(%RBP),%R12 |
0x4ea24e LEA 0x1(%R12),%R12 |
0x4ea253 JE 4eace0 |
0x4ea259 LEA (%RBX,%R12,1),%R10 |
0x4ea25d MOV 0x28(%RBP),%RAX |
0x4ea261 VMOVSD (%RAX,%R10,8),%XMM0 |
0x4ea267 MOV (%R14,%R10,8),%R13 |
0x4ea26b MOV 0x8(%R14,%R10,8),%RAX |
0x4ea270 MOV %RAX,%R8 |
0x4ea273 SUB %R13,%R8 |
0x4ea276 JLE 4ea240 |
0x4ea278 MOV %R8,%RSI |
0x4ea27b AND $-0x4,%RSI |
0x4ea27f JE 4ea300 |
0x4ea281 LEA -0x1(%RSI),%RBX |
0x4ea285 LEA (%R15,%R13,8),%RCX |
0x4ea289 LEA (%R11,%R13,8),%RDX |
0x4ea28d VXORPD %XMM1,%XMM1,%XMM1 |
0x4ea291 XOR %EDI,%EDI |
0x4ea293 NOPW %CS:(%RAX,%RAX,1) |
(3990) 0x4ea2a0 VMOVUPD (%RDX,%RDI,8),%YMM2 |
(3990) 0x4ea2a5 KXNORW %K0,%K0,%K1 |
(3990) 0x4ea2a9 VXORPD %XMM3,%XMM3,%XMM3 |
(3990) 0x4ea2ad VGATHERQPD (%R9,%YMM2,8),%YMM3{%K1} |
(3990) 0x4ea2b4 VFMADD231PD (%RCX,%RDI,8),%YMM3,%YMM1 |
(3990) 0x4ea2ba ADD $0x4,%RDI |
(3990) 0x4ea2be CMP %RBX,%RDI |
(3990) 0x4ea2c1 JBE 4ea2a0 |
0x4ea2c3 VEXTRACTF128 $0x1,%YMM1,%XMM2 |
0x4ea2c9 VADDPD %XMM2,%XMM1,%XMM1 |
0x4ea2cd VPERMILPD $0x1,%XMM1,%XMM2 |
0x4ea2d3 VADDSD %XMM2,%XMM1,%XMM1 |
0x4ea2d7 VADDSD %XMM1,%XMM0,%XMM0 |
0x4ea2db CMP %RSI,%R8 |
0x4ea2de MOV -0x38(%RBP),%RBX |
0x4ea2e2 JE 4ea240 |
0x4ea2e8 JMP 4ea302 |
0x4ea300 XOR %ESI,%ESI |
0x4ea302 ADD %R13,%RSI |
0x4ea305 NOPW %CS:(%RAX,%RAX,1) |
(3989) 0x4ea310 MOV (%R11,%RSI,8),%RCX |
(3989) 0x4ea314 VMOVSD (%R9,%RCX,8),%XMM1 |
(3989) 0x4ea31a VFMADD231SD (%R15,%RSI,8),%XMM1,%XMM0 |
(3989) 0x4ea320 INC %RSI |
(3989) 0x4ea323 CMP %RSI,%RAX |
(3989) 0x4ea326 JNE 4ea310 |
0x4ea328 JMP 4ea240 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 248 - 341 |
-------------------------------------------------------------------------------- |
248: hypre_assert(iBegin <= iEnd); |
[...] |
334: for (i = iBegin; i < iEnd; i++) |
335: { |
336: tempx = b_data[i]; |
337: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
338: { |
339: tempx += A_data[jj] * x_data[A_j[jj]]; |
340: } |
341: y_data[i] = tempx; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►96.61+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_CSRMatrixMatvecOutOfPlac[...] | csr_matvec.c:243 | exec |
| ○ | hypre_ParCSRMatrixMatvecOutOfP[...] | par_csr_matvec.c:216 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:456 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:545 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 | |
| ►3.39+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_CSRMatrixMatvecOutOfPlac[...] | csr_matvec.c:243 | exec |
| ○ | hypre_ParCSRMatrixMatvecOutOfP[...] | par_csr_matvec.c:216 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:456 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:424 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.04 |
| CQA speedup if FP arith vectorized | 1.89 |
| CQA speedup if fully vectorized | 9.72 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.71 |
| Bottlenecks | |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-341 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.00 |
| CQA cycles if no scalar integer | 2.94 |
| CQA cycles if FP arith vectorized | 3.17 |
| CQA cycles if fully vectorized | 0.62 |
| Front-end cycles | 6.00 |
| DIV/SQRT cycles | 3.38 |
| P0 cycles | 3.38 |
| P1 cycles | 3.25 |
| P2 cycles | 3.25 |
| P3 cycles | 1.00 |
| P4 cycles | 3.38 |
| P5 cycles | 3.38 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 8.14 |
| Stall cycles (UFS) | 1.79 |
| Nb insns | 24.25 |
| Nb uops | 24.00 |
| Nb loads | 6.50 |
| Nb stores | 1.00 |
| Nb stack references | 3.50 |
| FLOP/cycle | 0.33 |
| Nb FLOP add-sub | 2.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.48 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 52.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.50 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 3.50 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 17.69 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 19.44 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 25.71 |
| Vector-efficiency ratio all | 14.44 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 14.93 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 15.18 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.40 |
| Bottlenecks | micro-operation queue, P2, P3, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-341 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.00 |
| CQA cycles if no scalar integer | 1.50 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 0.38 |
| Front-end cycles | 3.00 |
| DIV/SQRT cycles | 1.25 |
| P0 cycles | 1.25 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.25 |
| P5 cycles | 1.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 3.16 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 13.00 |
| Nb uops | 12.00 |
| Nb loads | 6.00 |
| Nb stores | 1.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 18.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.22 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-341 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.00 |
| CQA cycles if no scalar integer | 2.25 |
| CQA cycles if FP arith vectorized | 5.00 |
| CQA cycles if fully vectorized | 0.63 |
| Front-end cycles | 5.00 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 2.50 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 2.50 |
| P5 cycles | 2.50 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 5.14 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 20.00 |
| Nb uops | 20.00 |
| Nb loads | 6.00 |
| Nb stores | 1.00 |
| Nb stack references | 3.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.20 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 48.00 |
| Bytes stored | 8.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 5.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.13 |
| CQA speedup if FP arith vectorized | 3.24 |
| CQA speedup if fully vectorized | 10.88 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.62 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-341 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.50 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 2.63 |
| CQA cycles if fully vectorized | 0.78 |
| Front-end cycles | 8.50 |
| DIV/SQRT cycles | 5.25 |
| P0 cycles | 5.25 |
| P1 cycles | 3.50 |
| P2 cycles | 3.50 |
| P3 cycles | 1.00 |
| P4 cycles | 5.25 |
| P5 cycles | 5.25 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 12.14 |
| Stall cycles (UFS) | 3.09 |
| Nb insns | 34.00 |
| Nb uops | 34.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 0.47 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 7.53 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 5.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 30.77 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 25.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 42.86 |
| Vector-efficiency ratio all | 15.87 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 15.63 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 16.96 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.88 |
| CQA speedup if FP arith vectorized | 3.64 |
| CQA speedup if fully vectorized | 10.91 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.67 |
| Bottlenecks | micro-operation queue, |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source | csr_matvec.c:248-341 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.50 |
| CQA cycles if no scalar integer | 4.00 |
| CQA cycles if FP arith vectorized | 2.06 |
| CQA cycles if fully vectorized | 0.69 |
| Front-end cycles | 7.50 |
| DIV/SQRT cycles | 4.50 |
| P0 cycles | 4.50 |
| P1 cycles | 3.50 |
| P2 cycles | 3.50 |
| P3 cycles | 1.00 |
| P4 cycles | 4.50 |
| P5 cycles | 4.50 |
| P6 cycles | 1.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 12.13 |
| Stall cycles (UFS) | 4.08 |
| Nb insns | 30.00 |
| Nb uops | 30.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 4.00 |
| FLOP/cycle | 0.53 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.53 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 8.00 |
| Stride 0 | 2.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 40.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 60.00 |
| Vector-efficiency ratio all | 16.88 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 16.67 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Path / |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-341 |
| Module | exec |
| nb instructions | 24.25 |
| nb uops | 24 |
| loop length | 107.25 |
| used x86 registers | 11.25 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0.50 |
| used zmm registers | 0 |
| nb stack references | 3.50 |
| micro-operation queue | 6.00 cycles |
| front end | 6.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 3.38 | 3.38 | 3.25 | 3.25 | 1.00 | 3.38 | 3.38 | 1.00 |
| cycles | 3.38 | 3.38 | 3.25 | 3.25 | 1.00 | 3.38 | 3.38 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 8.14 |
| Stall cycles | 1.79 |
| ROB full (events) | 2.02 |
| Front-end | 6.00 |
| Dispatch | 3.94 |
| Data deps. | 0.00 |
| Overall L1 | 6.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 25% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 17% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 19% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 11% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 16% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 14% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 15% |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-341 |
| Module | exec |
| nb instructions | 13 |
| nb uops | 12 |
| loop length | 56 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 3.00 cycles |
| front end | 3.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.25 | 1.25 | 3.00 | 3.00 | 1.00 | 1.25 | 1.25 | 1.00 |
| cycles | 1.25 | 1.25 | 3.00 | 3.00 | 1.00 | 1.25 | 1.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 3.16 |
| Stall cycles | 0.00 |
| Front-end | 3.00 |
| Dispatch | 3.00 |
| Data deps. | 0.00 |
| Overall L1 | 3.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RBX,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%RAX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%R10,8),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-341 |
| Module | exec |
| nb instructions | 20 |
| nb uops | 20 |
| loop length | 86 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 1 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 3 |
| micro-operation queue | 5.00 cycles |
| front end | 5.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 2.50 | 3.00 | 3.00 | 1.00 | 2.50 | 2.50 | 1.00 |
| cycles | 2.50 | 2.50 | 3.00 | 3.00 | 1.00 | 2.50 | 2.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 5.14 |
| Stall cycles | 0.00 |
| Front-end | 5.00 |
| Dispatch | 3.00 |
| Data deps. | 0.00 |
| Overall L1 | 5.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RBX,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%RAX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%R10,8),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4ea300 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| XOR %ESI,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| ADD %R13,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4ea240 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-341 |
| Module | exec |
| nb instructions | 34 |
| nb uops | 34 |
| loop length | 154 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 1 |
| used zmm registers | 0 |
| nb stack references | 4 |
| micro-operation queue | 8.50 cycles |
| front end | 8.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 5.25 | 5.25 | 3.50 | 3.50 | 1.00 | 5.25 | 5.25 | 1.00 |
| cycles | 5.25 | 5.25 | 3.50 | 3.50 | 1.00 | 5.25 | 5.25 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 12.14 |
| Stall cycles | 3.09 |
| ROB full (events) | 3.53 |
| Front-end | 8.50 |
| Dispatch | 5.25 |
| Data deps. | 0.00 |
| Overall L1 | 8.50 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 30% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 25% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 42% |
| all | 11% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 18% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 16% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 15% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 15% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 16% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RBX,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%RAX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%R10,8),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4ea300 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RSI),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R15,%R13,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R11,%R13,8),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPERMILPD $0x1,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RSI,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 4ea302 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| ADD %R13,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| JMP 4ea240 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| Function | hypre_CSRMatrixMatvecOutOfPlace.extracted |
| Source file and lines | csr_matvec.c:248-341 |
| Module | exec |
| nb instructions | 30 |
| nb uops | 30 |
| loop length | 133 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 1 |
| used zmm registers | 0 |
| nb stack references | 4 |
| micro-operation queue | 7.50 cycles |
| front end | 7.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 4.50 | 4.50 | 3.50 | 3.50 | 1.00 | 4.50 | 4.50 | 1.00 |
| cycles | 4.50 | 4.50 | 3.50 | 3.50 | 1.00 | 4.50 | 4.50 | 1.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 12.13 |
| Stall cycles | 4.08 |
| ROB full (events) | 4.54 |
| Front-end | 7.50 |
| Dispatch | 4.50 |
| Data deps. | 0.00 |
| Overall L1 | 7.50 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 50% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 40% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 60% |
| all | 9% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 18% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 16% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 16% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 16% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x30(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD %XMM0,(%RAX,%R10,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| CMP -0x30(%RBP),%R12 | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| LEA 0x1(%R12),%R12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| JE 4eace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA (%RBX,%R12,1),%R10 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV 0x28(%RBP),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%RAX,%R10,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV (%R14,%R10,8),%R13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV 0x8(%R14,%R10,8),%RAX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV %RAX,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| SUB %R13,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JLE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %R8,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| AND $-0x4,%RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 4ea300 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RSI),%RBX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R15,%R13,8),%RCX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA (%R11,%R13,8),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| NOPW %CS:(%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VEXTRACTF128 $0x1,%YMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 3 | 1 |
| VADDPD %XMM2,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPERMILPD $0x1,%XMM1,%XMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VADDSD %XMM2,%XMM1,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM1,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RSI,%R8 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| MOV -0x38(%RBP),%RBX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| JE 4ea240 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
