| Loop Id: 684 | Module: exec | Source: par_multi_interp.c:275-276 | Coverage: 0.01% |
|---|
| Loop Id: 684 | Module: exec | Source: par_multi_interp.c:275-276 | Coverage: 0.01% |
|---|
0x474b99 VMOVDQU64 (%R13),%ZMM15 [1] |
0x474ba0 VMOVDQU64 0x40(%R13),%ZMM9 [1] |
0x474ba7 ADD $0x200,%R13 |
0x474bae VPCMPEQQ %ZMM5,%ZMM15,%K1 |
0x474bb5 VPCMPEQQ %ZMM4,%ZMM15,%K2 |
0x474bbc VPCMPEQQ %ZMM4,%ZMM9,%K4 |
0x474bc3 VPCMPEQQ %ZMM5,%ZMM9,%K3 |
0x474bca VMOVDQA64 %ZMM3,%ZMM1{%K1}{z} |
0x474bd0 VMOVDQA64 %ZMM3,%ZMM6{%K2}{z} |
0x474bd6 VPSUBQ %ZMM1,%ZMM2,%ZMM7 |
0x474bdc VPSUBQ %ZMM6,%ZMM0,%ZMM8 |
0x474be2 VMOVDQU64 -0x180(%R13),%ZMM2 [2] |
0x474be9 VMOVDQA64 %ZMM3,%ZMM12{%K4}{z} |
0x474bef VPSUBQ %ZMM12,%ZMM8,%ZMM13 |
0x474bf5 VMOVDQU64 -0x140(%R13),%ZMM8 [2] |
0x474bfc VMOVDQA64 %ZMM3,%ZMM10{%K3}{z} |
0x474c02 VPCMPEQQ %ZMM5,%ZMM2,%K5 |
0x474c09 VPCMPEQQ %ZMM4,%ZMM2,%K6 |
0x474c10 VPSUBQ %ZMM10,%ZMM7,%ZMM11 |
0x474c16 VPCMPEQQ %ZMM5,%ZMM8,%K7 |
0x474c1d VPCMPEQQ %ZMM4,%ZMM8,%K1 |
0x474c24 VMOVDQA64 %ZMM3,%ZMM14{%K5}{z} |
0x474c2a VMOVDQA64 %ZMM3,%ZMM0{%K6}{z} |
0x474c30 VPSUBQ %ZMM14,%ZMM11,%ZMM15 |
0x474c36 VMOVDQA64 %ZMM3,%ZMM1{%K7}{z} |
0x474c3c VMOVDQU64 -0x100(%R13),%ZMM11 [2] |
0x474c43 VPSUBQ %ZMM0,%ZMM13,%ZMM7 |
0x474c49 VPSUBQ %ZMM1,%ZMM15,%ZMM9 |
0x474c4f VMOVDQU64 -0xc0(%R13),%ZMM15 [2] |
0x474c56 VMOVDQA64 %ZMM3,%ZMM6{%K1}{z} |
0x474c5c VPCMPEQQ %ZMM5,%ZMM11,%K2 |
0x474c63 VPCMPEQQ %ZMM4,%ZMM11,%K3 |
0x474c6a VPSUBQ %ZMM6,%ZMM7,%ZMM10 |
0x474c70 VPCMPEQQ %ZMM5,%ZMM15,%K4 |
0x474c77 VPCMPEQQ %ZMM4,%ZMM15,%K5 |
0x474c7e VMOVDQA64 %ZMM3,%ZMM12{%K2}{z} |
0x474c84 VMOVDQA64 %ZMM3,%ZMM2{%K3}{z} |
0x474c8a VPSUBQ %ZMM12,%ZMM9,%ZMM13 |
0x474c90 VPSUBQ %ZMM2,%ZMM10,%ZMM14 |
0x474c96 VMOVDQA64 %ZMM3,%ZMM0{%K4}{z} |
0x474c9c VMOVDQU64 -0x80(%R13),%ZMM10 [2] |
0x474ca3 VPSUBQ %ZMM0,%ZMM13,%ZMM7 |
0x474ca9 VMOVDQU64 -0x40(%R13),%ZMM13 [2] |
0x474cb0 VMOVDQA64 %ZMM3,%ZMM8{%K5}{z} |
0x474cb6 VPCMPEQQ %ZMM5,%ZMM10,%K6 |
0x474cbd VPCMPEQQ %ZMM4,%ZMM10,%K7 |
0x474cc4 VPSUBQ %ZMM8,%ZMM14,%ZMM9 |
0x474cca VPCMPEQQ %ZMM5,%ZMM13,%K1 |
0x474cd1 VPCMPEQQ %ZMM4,%ZMM13,%K2 |
0x474cd8 VMOVDQA64 %ZMM3,%ZMM1{%K6}{z} |
0x474cde VMOVDQA64 %ZMM3,%ZMM6{%K7}{z} |
0x474ce4 VPSUBQ %ZMM1,%ZMM7,%ZMM11 |
0x474cea VPSUBQ %ZMM6,%ZMM9,%ZMM12 |
0x474cf0 VMOVDQA64 %ZMM3,%ZMM2{%K1}{z} |
0x474cf6 VMOVDQA64 %ZMM3,%ZMM14{%K2}{z} |
0x474cfc VPSUBQ %ZMM2,%ZMM11,%ZMM2 |
0x474d02 VPSUBQ %ZMM14,%ZMM12,%ZMM0 |
0x474d08 CMP %R10,%R13 |
0x474d0b JNE 474b99 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_multi_interp.c: 275 - 276 |
-------------------------------------------------------------------------------- |
275: if (CF_marker[i] == 1) n_coarse++; |
276: else if (CF_marker[i] == -3) n_SF++; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.10 |
| Bottlenecks | P0, P5, |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
| Source | par_multi_interp.c:275-276 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 14.50 |
| DIV/SQRT cycles | 16.00 |
| P0 cycles | 1.00 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 0.00 |
| P4 cycles | 16.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 16.10 |
| Stall cycles (UFS) | 1.14 |
| Nb insns | 59.00 |
| Nb uops | 58.00 |
| Nb loads | 8.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 32.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.10 |
| Bottlenecks | P0, P5, |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
| Source | par_multi_interp.c:275-276 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 14.50 |
| DIV/SQRT cycles | 16.00 |
| P0 cycles | 1.00 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 0.00 |
| P4 cycles | 16.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 16.10 |
| Stall cycles (UFS) | 1.14 |
| Nb insns | 59.00 |
| Nb uops | 58.00 |
| Nb loads | 8.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 32.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
| Source file and lines | par_multi_interp.c:275-276 |
| Module | exec |
| nb instructions | 59 |
| nb uops | 58 |
| loop length | 376 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 0 |
| micro-operation queue | 14.50 cycles |
| front end | 14.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 16.00 | 1.00 | 4.00 | 4.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| cycles | 16.00 | 1.00 | 4.00 | 4.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 16.10 |
| Stall cycles | 1.14 |
| RS full (events) | 2.28 |
| Front-end | 14.50 |
| Dispatch | 16.00 |
| Data deps. | 8.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 (%R13),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU64 0x40(%R13),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| ADD $0x200,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM15,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM15,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM9,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM5,%ZMM9,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM1{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM6{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM1,%ZMM2,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM6,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x180(%R13),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM12{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM12,%ZMM8,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x140(%R13),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM10{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM2,%K5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM10,%ZMM7,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM8,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM14{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM0{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM14,%ZMM11,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM1{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQU64 -0x100(%R13),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VPSUBQ %ZMM0,%ZMM13,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM1,%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0xc0(%R13),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM6{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM11,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM11,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM6,%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM15,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM15,%K5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM12{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM2{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM12,%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM2,%ZMM10,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM0{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQU64 -0x80(%R13),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VPSUBQ %ZMM0,%ZMM13,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x40(%R13),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM8{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM10,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM10,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM8,%ZMM14,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM13,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM13,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM1{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM6{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM1,%ZMM7,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM6,%ZMM9,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM2{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM14{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM2,%ZMM11,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM14,%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R10,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 474b99 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_BoomerAMGBuildMultipass._omp_fn.0 |
| Source file and lines | par_multi_interp.c:275-276 |
| Module | exec |
| nb instructions | 59 |
| nb uops | 58 |
| loop length | 376 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 0 |
| micro-operation queue | 14.50 cycles |
| front end | 14.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 16.00 | 1.00 | 4.00 | 4.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| cycles | 16.00 | 1.00 | 4.00 | 4.00 | 0.00 | 16.00 | 1.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 16.10 |
| Stall cycles | 1.14 |
| RS full (events) | 2.28 |
| Front-end | 14.50 |
| Dispatch | 16.00 |
| Data deps. | 8.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQU64 (%R13),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU64 0x40(%R13),%ZMM9 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| ADD $0x200,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM15,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM15,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM9,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM5,%ZMM9,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM1{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM6{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM1,%ZMM2,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM6,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x180(%R13),%ZMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM12{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM12,%ZMM8,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x140(%R13),%ZMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM10{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM2,%K5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM2,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM10,%ZMM7,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM8,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM14{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM0{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM14,%ZMM11,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM1{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQU64 -0x100(%R13),%ZMM11 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VPSUBQ %ZMM0,%ZMM13,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM1,%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0xc0(%R13),%ZMM15 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM6{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM11,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM11,%K3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM6,%ZMM7,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM15,%K4 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM15,%K5 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM12{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM2{%K3}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM12,%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM2,%ZMM10,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM0{%K4}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQU64 -0x80(%R13),%ZMM10 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VPSUBQ %ZMM0,%ZMM13,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQU64 -0x40(%R13),%ZMM13 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM8{%K5}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPCMPEQQ %ZMM5,%ZMM10,%K6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM10,%K7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPSUBQ %ZMM8,%ZMM14,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPCMPEQQ %ZMM5,%ZMM13,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VPCMPEQQ %ZMM4,%ZMM13,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 |
| VMOVDQA64 %ZMM3,%ZMM1{%K6}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM6{%K7}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM1,%ZMM7,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM6,%ZMM9,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVDQA64 %ZMM3,%ZMM2{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VMOVDQA64 %ZMM3,%ZMM14{%K2}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 |
| VPSUBQ %ZMM2,%ZMM11,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| VPSUBQ %ZMM14,%ZMM12,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %R10,%R13 | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 474b99 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
