| Loop Id: 3938 | Module: exec | Source: csr_matvec.c:612-615 | Coverage: 0.18% |
|---|
| Loop Id: 3938 | Module: exec | Source: csr_matvec.c:612-615 | Coverage: 0.18% |
|---|
0x4d3dc0 VMOVSD (%R15,%RDX,8),%XMM0 [6] |
0x4d3dc6 VMOVSD -0x18(%R12,%RAX,1),%XMM1 [2] |
0x4d3dcd MOV -0x18(%R13,%RAX,1),%RCX [5] |
0x4d3dd2 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 [4] |
0x4d3dd8 VMOVSD %XMM1,(%RBX,%RCX,8) [4] |
0x4d3ddd MOV -0x10(%R13,%RAX,1),%RCX [5] |
0x4d3de2 VMOVSD (%R15,%RDX,8),%XMM0 [6] |
0x4d3de8 VMOVSD -0x10(%R12,%RAX,1),%XMM1 [2] |
0x4d3def VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 [1] |
0x4d3df5 VMOVSD %XMM1,(%RBX,%RCX,8) [1] |
0x4d3dfa MOV -0x8(%R13,%RAX,1),%RCX [5] |
0x4d3dff VMOVSD (%R15,%RDX,8),%XMM0 [6] |
0x4d3e05 VMOVSD -0x8(%R12,%RAX,1),%XMM1 [2] |
0x4d3e0c VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 [3] |
0x4d3e12 VMOVSD %XMM1,(%RBX,%RCX,8) [3] |
0x4d3e17 MOV (%R13,%RAX,1),%RCX [5] |
0x4d3e1c VMOVSD (%R15,%RDX,8),%XMM0 [6] |
0x4d3e22 VMOVSD (%R12,%RAX,1),%XMM1 [2] |
0x4d3e28 VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 [7] |
0x4d3e2e VMOVSD %XMM1,(%RBX,%RCX,8) [7] |
0x4d3e33 ADD $0x20,%RAX |
0x4d3e37 DEC %RDI |
0x4d3e3a JNE 4d3dc0 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/seq_mv/csr_matvec.c: 612 - 615 |
-------------------------------------------------------------------------------- |
612: for (jj = A_i[i]; jj < A_i[i+1]; jj++) |
613: { |
614: j = A_j[jj]; |
615: y_data[j] += A_data[jj] * x_data[i]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | hypre_ParCSRMatrixMatvecT | par_csr_matvec.c:432 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:435 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:545 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.33 |
| CQA speedup if FP arith vectorized | 1.28 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P2, P3, |
| Function | hypre_CSRMatrixMatvecT |
| Source | csr_matvec.c:612-615 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.25 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 6.50 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 4.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 4.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.20 |
| Stall cycles (UFS) | 1.49 |
| Nb insns | 23.00 |
| Nb uops | 22.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 32.00 |
| Stride 0 | 1.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.33 |
| CQA speedup if FP arith vectorized | 1.28 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P2, P3, |
| Function | hypre_CSRMatrixMatvecT |
| Source | csr_matvec.c:612-615 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 6.00 |
| CQA cycles if FP arith vectorized | 6.25 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 6.50 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 8.00 |
| P2 cycles | 8.00 |
| P3 cycles | 4.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 4.00 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.20 |
| Stall cycles (UFS) | 1.49 |
| Nb insns | 23.00 |
| Nb uops | 22.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 32.00 |
| Stride 0 | 1.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | hypre_CSRMatrixMatvecT |
| Source file and lines | csr_matvec.c:612-615 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 22 |
| loop length | 124 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 8.00 | 8.00 | 4.00 | 1.00 | 1.00 | 4.00 |
| cycles | 2.00 | 2.00 | 8.00 | 8.00 | 4.00 | 1.00 | 1.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.20 |
| Stall cycles | 1.49 |
| LM full (events) | 2.98 |
| Front-end | 6.50 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x18(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x18(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x10(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x10(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x8(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x8(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV (%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x20,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4d3dc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_CSRMatrixMatvecT |
| Source file and lines | csr_matvec.c:612-615 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 22 |
| loop length | 124 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.50 cycles |
| front end | 6.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 8.00 | 8.00 | 4.00 | 1.00 | 1.00 | 4.00 |
| cycles | 2.00 | 2.00 | 8.00 | 8.00 | 4.00 | 1.00 | 1.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.20 |
| Stall cycles | 1.49 |
| LM full (events) | 2.98 |
| Front-end | 6.50 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 0% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 12% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x18(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| MOV -0x18(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x10(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x10(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV -0x8(%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD -0x8(%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV (%R13,%RAX,1),%RCX | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R15,%RDX,8),%XMM0 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVSD (%R12,%RAX,1),%XMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VFMADD213SD (%RBX,%RCX,8),%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM1,(%RBX,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| ADD $0x20,%RAX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 4d3dc0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
