| Loop Id: 4219 | Module: exec | Source: :0-0 | Coverage: 1.47% |
|---|
| Loop Id: 4219 | Module: exec | Source: :0-0 | Coverage: 1.47% |
|---|
0x4fcfb0 PREFETCHT0 0x200(%RSI) [2] |
0x4fcfb7 PREFETCHT0 0x240(%RSI) [2] |
0x4fcfbe PREFETCHT0 0x280(%RSI) [2] |
0x4fcfc5 PREFETCHT0 0x2c0(%RSI) [2] |
0x4fcfcc VMOVDQU (%RSI),%YMM1 [2] |
0x4fcfd0 VMOVDQU 0x20(%RSI),%YMM2 [2] |
0x4fcfd5 VMOVDQU 0x40(%RSI),%YMM3 [2] |
0x4fcfda VMOVDQU 0x60(%RSI),%YMM4 [2] |
0x4fcfdf VMOVDQU 0x80(%RSI),%YMM5 [2] |
0x4fcfe7 VMOVDQU 0xa0(%RSI),%YMM6 [2] |
0x4fcfef VMOVDQU 0xc0(%RSI),%YMM7 [2] |
0x4fcff7 VMOVDQU 0xe0(%RSI),%YMM8 [2] |
0x4fcfff SUB $0x100,%RCX |
0x4fd006 VMOVNTDQ %YMM1,(%RDI) [1] |
0x4fd00a VMOVNTDQ %YMM2,0x20(%RDI) [1] |
0x4fd00f VMOVNTDQ %YMM3,0x40(%RDI) [1] |
0x4fd014 VMOVNTDQ %YMM4,0x60(%RDI) [1] |
0x4fd019 VMOVNTDQ %YMM5,0x80(%RDI) [1] |
0x4fd021 VMOVNTDQ %YMM6,0xa0(%RDI) [1] |
0x4fd029 VMOVNTDQ %YMM7,0xc0(%RDI) [1] |
0x4fd031 VMOVNTDQ %YMM8,0xe0(%RDI) [1] |
0x4fd039 LEA 0x100(%RDI),%RDI |
0x4fd040 LEA 0x100(%RSI),%RSI |
0x4fd047 CMP $0x300,%RCX |
0x4fd04e JGE 4fcfb0 |
*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►91.89+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_SeqVectorCopy | vector.c:343 | exec |
| ○ | hypre_ParCSRRelax | ams.c:75 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:322 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:545 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 | |
| ►3.60+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_SeqVectorCopy | vector.c:343 | exec |
| ○ | hypre_ParCSRRelax | ams.c:75 | exec |
| ○ | hypre_BoomerAMGCycle | par_cycle.c:322 | exec |
| ○ | hypre_BoomerAMGSolve | par_amg_solve.c:272 | exec |
| ○ | hypre_PCGSolve | pcg.c:424 | exec |
| ○ | main | amg.c:419 | exec |
| ○ | __libc_init_first | libc.so.6 | |
| ►1.80+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_IJMatrixInitializeParCSR | IJMatrix_parcsr.c:302 | exec |
| ○ | HYPRE_IJMatrixInitialize | HYPRE_IJMatrix.c:292 | exec |
| ○ | BuildIJLaplacian27pt | amg.c:2262 | exec |
| ○ | main | amg.c:274 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.20 |
| Bottlenecks | P4, |
| Function | __intel_avx_rep_memcpy |
| Source | |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 6.00 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.25 |
| P1 cycles | 6.67 |
| P2 cycles | 6.67 |
| P3 cycles | 8.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 6.67 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.12 |
| Stall cycles (UFS) | 1.76 |
| Nb insns | 25.00 |
| Nb uops | 24.00 |
| Nb loads | 12.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 256.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.20 |
| Bottlenecks | P4, |
| Function | __intel_avx_rep_memcpy |
| Source | |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 4.00 |
| Front-end cycles | 6.00 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.25 |
| P1 cycles | 6.67 |
| P2 cycles | 6.67 |
| P3 cycles | 8.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.00 |
| P6 cycles | 6.67 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.12 |
| Stall cycles (UFS) | 1.76 |
| Nb insns | 25.00 |
| Nb uops | 24.00 |
| Nb loads | 12.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 64.00 |
| Bytes prefetched | 256.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | __intel_avx_rep_memcpy |
| Source file and lines | |
| Module | exec |
| nb instructions | 25 |
| nb uops | 24 |
| loop length | 164 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 8 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.00 cycles |
| front end | 6.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 6.67 | 6.67 | 8.00 | 1.00 | 1.00 | 6.67 |
| cycles | 1.00 | 1.25 | 6.67 | 6.67 | 8.00 | 1.00 | 1.00 | 6.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.12 |
| Stall cycles | 1.76 |
| LB full (events) | 1.68 |
| LM full (events) | 0.21 |
| Front-end | 6.00 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PREFETCHT0 0x200(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x240(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x280(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x2c0(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVDQU (%RSI),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x20(%RSI),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x40(%RSI),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x60(%RSI),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x80(%RSI),%YMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xa0(%RSI),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xc0(%RSI),%YMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xe0(%RSI),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| SUB $0x100,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVNTDQ %YMM1,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM2,0x20(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM3,0x40(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM4,0x60(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM5,0x80(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM6,0xa0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM7,0xc0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM8,0xe0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| LEA 0x100(%RDI),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA 0x100(%RSI),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP $0x300,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 4fcfb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | __intel_avx_rep_memcpy |
| Source file and lines | |
| Module | exec |
| nb instructions | 25 |
| nb uops | 24 |
| loop length | 164 |
| used x86 registers | 3 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 8 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 6.00 cycles |
| front end | 6.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 6.67 | 6.67 | 8.00 | 1.00 | 1.00 | 6.67 |
| cycles | 1.00 | 1.25 | 6.67 | 6.67 | 8.00 | 1.00 | 1.00 | 6.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.12 |
| Stall cycles | 1.76 |
| LB full (events) | 1.68 |
| LM full (events) | 0.21 |
| Front-end | 6.00 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| PREFETCHT0 0x200(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x240(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x280(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| PREFETCHT0 0x2c0(%RSI) | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 4-5 | 0.50 |
| VMOVDQU (%RSI),%YMM1 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x20(%RSI),%YMM2 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x40(%RSI),%YMM3 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x60(%RSI),%YMM4 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0x80(%RSI),%YMM5 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xa0(%RSI),%YMM6 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xc0(%RSI),%YMM7 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| VMOVDQU 0xe0(%RSI),%YMM8 | 1 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 5 | 0.50 |
| SUB $0x100,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| VMOVNTDQ %YMM1,(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM2,0x20(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM3,0x40(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM4,0x60(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM5,0x80(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM6,0xa0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM7,0xc0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| VMOVNTDQ %YMM8,0xe0(%RDI) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 400 | 1 |
| LEA 0x100(%RDI),%RDI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| LEA 0x100(%RSI),%RSI | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP $0x300,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JGE 4fcfb0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
