| Loop Id: 2324 | Module: exec | Source: par_strength.c:1268-1278 | Coverage: 0.01% |
|---|
| Loop Id: 2324 | Module: exec | Source: par_strength.c:1268-1278 | Coverage: 0.01% |
|---|
0x48ace0 MOVQ $-0x1,(%R14,%RCX,8) [2] |
0x48ace8 ADD $0x4,%RCX |
0x48acec DEC %RDI |
0x48acef JE 48ad9e |
0x48acf5 CMPQ $0,-0x18(%RBX,%RCX,8) [1] |
0x48acfb JLE 48ad50 |
0x48acfd LEA -0x3(%RCX),%RDX |
0x48ad01 MOV %RSI,-0x18(%R14,%RCX,8) [2] |
0x48ad06 MOV %RDX,(%R10,%RSI,8) [6] |
0x48ad0a INC %RSI |
0x48ad0d CMPQ $0,-0x10(%RBX,%RCX,8) [1] |
0x48ad13 JLE 48ad61 |
0x48ad15 LEA -0x2(%RCX),%RDX |
0x48ad19 MOV %RSI,-0x10(%R14,%RCX,8) [2] |
0x48ad1e MOV %RDX,(%R10,%RSI,8) [3] |
0x48ad22 INC %RSI |
0x48ad25 CMPQ $0,-0x8(%RBX,%RCX,8) [1] |
0x48ad2b JLE 48ad72 |
0x48ad2d LEA -0x1(%RCX),%RDX |
0x48ad31 MOV %RSI,-0x8(%R14,%RCX,8) [2] |
0x48ad36 MOV %RDX,(%R10,%RSI,8) [4] |
0x48ad3a INC %RSI |
0x48ad3d CMPQ $0,(%RBX,%RCX,8) [1] |
0x48ad42 JG 48ad86 |
0x48ad44 JMP 48ace0 |
0x48ad50 MOVQ $-0x1,-0x18(%R14,%RCX,8) [2] |
0x48ad59 CMPQ $0,-0x10(%RBX,%RCX,8) [1] |
0x48ad5f JG 48ad15 |
0x48ad61 MOVQ $-0x1,-0x10(%R14,%RCX,8) [2] |
0x48ad6a CMPQ $0,-0x8(%RBX,%RCX,8) [1] |
0x48ad70 JG 48ad2d |
0x48ad72 MOVQ $-0x1,-0x8(%R14,%RCX,8) [2] |
0x48ad7b CMPQ $0,(%RBX,%RCX,8) [1] |
0x48ad80 JLE 48ace0 |
0x48ad86 MOV %RSI,(%R14,%RCX,8) [2] |
0x48ad8a MOV %RCX,(%R10,%RSI,8) [5] |
0x48ad8e INC %RSI |
0x48ad91 ADD $0x4,%RCX |
0x48ad95 DEC %RDI |
0x48ad98 JNE 48acf5 |
/home/kcamus/qaas_runs/169-443-9681/intel/AMG/build/AMG/AMG/parcsr_ls/par_strength.c: 1268 - 1278 |
-------------------------------------------------------------------------------- |
1268: for (i = i_begin; i < i_end; i++) |
1269: { |
1270: if (CF_marker[i] > 0) |
1271: { |
1272: fine_to_coarse[i] = num_coarse_private; |
1273: coarse_to_fine[num_coarse_private] = i; |
1274: num_coarse_private++; |
1275: } |
1276: else |
1277: { |
1278: fine_to_coarse[i] = -1; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_fork_call | libiomp5.so | |
| ○ | __kmpc_fork_call | libiomp5.so | |
| ○ | hypre_BoomerAMGCreate2ndS | par_strength.c:1253 | exec |
| ○ | hypre_BoomerAMGSetup | par_amg_setup.c:617 | exec |
| ○ | hypre_PCGSetup | pcg.c:234 | exec |
| ○ | main | amg.c:398 | exec |
| ○ | __libc_init_first | libc.so.6 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 9.60 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGCreate2ndS.extracted |
| Source | par_strength.c:1268-1278 |
| Source loop unroll info | unrolled by 6 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 6 |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 12.00 |
| CQA cycles if fully vectorized | 1.25 |
| Front-end cycles | 9.75 |
| DIV/SQRT cycles | 6.75 |
| P0 cycles | 6.75 |
| P1 cycles | 6.50 |
| P2 cycles | 6.17 |
| P3 cycles | 12.00 |
| P4 cycles | 6.75 |
| P5 cycles | 6.75 |
| P6 cycles | 6.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 12.08 |
| Stall cycles (UFS) | 1.88 |
| Nb insns | 40.00 |
| Nb uops | 39.00 |
| Nb loads | 7.00 |
| Nb stores | 12.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 96.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 11.18 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 10.42 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 9.60 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.23 |
| Bottlenecks | P4, |
| Function | hypre_BoomerAMGCreate2ndS.extracted |
| Source | par_strength.c:1268-1278 |
| Source loop unroll info | unrolled by 6 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 6 |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 12.00 |
| CQA cycles if fully vectorized | 1.25 |
| Front-end cycles | 9.75 |
| DIV/SQRT cycles | 6.75 |
| P0 cycles | 6.75 |
| P1 cycles | 6.50 |
| P2 cycles | 6.17 |
| P3 cycles | 12.00 |
| P4 cycles | 6.75 |
| P5 cycles | 6.75 |
| P6 cycles | 6.33 |
| P7 cycles | 0.00 |
| Inter-iter dependencies cycles | NA |
| FE+BE cycles (UFS) | 12.08 |
| Stall cycles (UFS) | 1.88 |
| Nb insns | 40.00 |
| Nb uops | 39.00 |
| Nb loads | 7.00 |
| Nb stores | 12.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 96.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 11.18 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 10.42 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | hypre_BoomerAMGCreate2ndS.extracted |
| Source file and lines | par_strength.c:1268-1278 |
| Module | exec |
| nb instructions | 40 |
| nb uops | 39 |
| loop length | 180 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 6.75 | 6.75 | 6.50 | 6.17 | 12.00 | 6.75 | 6.75 | 6.33 |
| cycles | 6.75 | 6.75 | 6.50 | 6.17 | 12.00 | 6.75 | 6.75 | 6.33 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 12.08 |
| Stall cycles | 1.88 |
| SB full (events) | 4.18 |
| Front-end | 9.75 |
| Dispatch | 12.00 |
| Overall L1 | 12.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 11% |
| load | 12% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOVQ $-0x1,(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| ADD $0x4,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 48ad9e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0,-0x18(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad50 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x3(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x18(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,-0x10(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad61 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x2(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x10(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,-0x8(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad72 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x8(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad86 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 48ace0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| MOVQ $-0x1,-0x18(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,-0x10(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOVQ $-0x1,-0x10(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,-0x8(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad2d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOVQ $-0x1,-0x8(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %RSI,(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RCX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD $0x4,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 48acf5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| Function | hypre_BoomerAMGCreate2ndS.extracted |
| Source file and lines | par_strength.c:1268-1278 |
| Module | exec |
| nb instructions | 40 |
| nb uops | 39 |
| loop length | 180 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.75 cycles |
| front end | 9.75 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | |
|---|---|---|---|---|---|---|---|---|
| uops | 6.75 | 6.75 | 6.50 | 6.17 | 12.00 | 6.75 | 6.75 | 6.33 |
| cycles | 6.75 | 6.75 | 6.50 | 6.17 | 12.00 | 6.75 | 6.75 | 6.33 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 12.08 |
| Stall cycles | 1.88 |
| SB full (events) | 4.18 |
| Front-end | 9.75 |
| Dispatch | 12.00 |
| Overall L1 | 12.00 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 11% |
| load | 12% |
| store | 10% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|
| MOVQ $-0x1,(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| ADD $0x4,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JE 48ad9e | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| CMPQ $0,-0x18(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad50 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x3(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x18(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,-0x10(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad61 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x2(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x10(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,-0x8(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ad72 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| LEA -0x1(%RCX),%RDX | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,-0x8(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RDX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| CMPQ $0,(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad86 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| JMP 48ace0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1-2 |
| MOVQ $-0x1,-0x18(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,-0x10(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOVQ $-0x1,-0x10(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,-0x8(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JG 48ad2d | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOVQ $-0x1,-0x8(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 2 | 1 |
| CMPQ $0,(%RBX,%RCX,8) | 1 | 0.25 | 0.25 | 0.50 | 0.50 | 0 | 0.25 | 0.25 | 0 | 1 | 0.50 |
| JLE 48ace0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
| MOV %RSI,(%R14,%RCX,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| MOV %RCX,(%R10,%RSI,8) | 1 | 0 | 0 | 0.33 | 0.33 | 1 | 0 | 0 | 0.33 | 3 | 1 |
| INC %RSI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| ADD $0x4,%RCX | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| DEC %RDI | 1 | 0.25 | 0.25 | 0 | 0 | 0 | 0.25 | 0.25 | 0 | 1 | 0.25 |
| JNE 48acf5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50-1 |
