| Loop Id: 146 | Module: exec | Source: advec_mom_kernel.f90:131-131 | Coverage: 0.96% |
|---|
| Loop Id: 146 | Module: exec | Source: advec_mom_kernel.f90:131-131 | Coverage: 0.96% |
|---|
0x43642a VMOVUPD (%R14,%RCX,1),%ZMM3 [6] |
0x436431 VMOVUPD (%R11,%RCX,1),%ZMM7 [3] |
0x436438 VADDPD (%RSI,%RCX,1),%ZMM3,%ZMM2 [5] |
0x43643f VADDPD (%RBX,%RCX,1),%ZMM7,%ZMM0 [2] |
0x436446 VADDPD %ZMM0,%ZMM2,%ZMM14 |
0x43644c VMULPD %ZMM12,%ZMM14,%ZMM6 |
0x436452 VMOVUPD %ZMM6,(%R12,%RCX,1) [1] |
0x436459 VMOVUPD 0x40(%R14,%RCX,1),%ZMM4 [6] |
0x436461 VMOVUPD 0x40(%R11,%RCX,1),%ZMM13 [3] |
0x436469 VADDPD 0x40(%RCX,%RSI,1),%ZMM4,%ZMM9 [4] |
0x436471 VADDPD 0x40(%RBX,%RCX,1),%ZMM13,%ZMM15 [2] |
0x436479 VADDPD %ZMM15,%ZMM9,%ZMM1 |
0x43647f VMULPD %ZMM12,%ZMM1,%ZMM5 |
0x436485 VMOVUPD %ZMM5,0x40(%R12,%RCX,1) [1] |
0x43648d VMOVUPD 0x80(%R14,%RCX,1),%ZMM8 [6] |
0x436495 VMOVUPD 0x80(%R11,%RCX,1),%ZMM2 [3] |
0x43649d VADDPD 0x80(%RCX,%RSI,1),%ZMM8,%ZMM3 [4] |
0x4364a5 VADDPD 0x80(%RBX,%RCX,1),%ZMM2,%ZMM7 [2] |
0x4364ad VADDPD %ZMM7,%ZMM3,%ZMM0 |
0x4364b3 VMULPD %ZMM12,%ZMM0,%ZMM14 |
0x4364b9 VMOVUPD %ZMM14,0x80(%R12,%RCX,1) [1] |
0x4364c1 VMOVUPD 0xc0(%R14,%RCX,1),%ZMM6 [6] |
0x4364c9 VMOVUPD 0xc0(%R11,%RCX,1),%ZMM9 [3] |
0x4364d1 VADDPD 0xc0(%RCX,%RSI,1),%ZMM6,%ZMM4 [4] |
0x4364d9 VADDPD 0xc0(%RBX,%RCX,1),%ZMM9,%ZMM13 [2] |
0x4364e1 VADDPD %ZMM13,%ZMM4,%ZMM15 |
0x4364e7 VMULPD %ZMM12,%ZMM15,%ZMM1 |
0x4364ed VMOVUPD %ZMM1,0xc0(%R12,%RCX,1) [1] |
0x4364f5 ADD $0x100,%RCX |
0x4364fc CMP %R15,%RCX |
0x4364ff JNE 43642a |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 131 - 131 |
-------------------------------------------------------------------------------- |
131: +mass_flux_x(j+1,k-1)+mass_flux_x(j+1,k)) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:131-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 2.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.40 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.23 |
| Stall cycles (UFS) | 1.19 |
| Nb insns | 31.00 |
| Nb uops | 30.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 16.00 |
| Nb FLOP add-sub | 96.00 |
| Nb FLOP mul | 32.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 160.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1024.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 4.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:131-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 2.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.40 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.23 |
| Stall cycles (UFS) | 1.19 |
| Nb insns | 31.00 |
| Nb uops | 30.00 |
| Nb loads | 16.00 |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 16.00 |
| Nb FLOP add-sub | 96.00 |
| Nb FLOP mul | 32.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 160.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1024.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 4.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:131-131 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 30 |
| loop length | 219 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.60 | 5.33 | 5.33 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 5.33 |
| cycles | 8.00 | 8.00 | 5.33 | 5.33 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.23 |
| Stall cycles | 1.19 |
| RS full (events) | 4.79 |
| Front-end | 6.33 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R14,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R11,%RCX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD (%RSI,%RCX,1),%ZMM3,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RBX,%RCX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM0,%ZMM2,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM14,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM6,(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R14,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R11,%RCX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0x40(%RCX,%RSI,1),%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0x40(%RBX,%RCX,1),%ZMM13,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM15,%ZMM9,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM5,0x40(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x80(%R14,%RCX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x80(%R11,%RCX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0x80(%RCX,%RSI,1),%ZMM8,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0x80(%RBX,%RCX,1),%ZMM2,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM7,%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM0,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM14,0x80(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0xc0(%R14,%RCX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0xc0(%R11,%RCX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0xc0(%RCX,%RSI,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0xc0(%RBX,%RCX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM13,%ZMM4,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM1,0xc0(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 43642a <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x420a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:131-131 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 30 |
| loop length | 219 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.60 | 5.33 | 5.33 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 5.33 |
| cycles | 8.00 | 8.00 | 5.33 | 5.33 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.40 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.23 |
| Stall cycles | 1.19 |
| RS full (events) | 4.79 |
| Front-end | 6.33 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R14,%RCX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R11,%RCX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD (%RSI,%RCX,1),%ZMM3,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RBX,%RCX,1),%ZMM7,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM0,%ZMM2,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM14,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM6,(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R14,%RCX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R11,%RCX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0x40(%RCX,%RSI,1),%ZMM4,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0x40(%RBX,%RCX,1),%ZMM13,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM15,%ZMM9,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM5,0x40(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x80(%R14,%RCX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x80(%R11,%RCX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0x80(%RCX,%RSI,1),%ZMM8,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0x80(%RBX,%RCX,1),%ZMM2,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM7,%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM0,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM14,0x80(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0xc0(%R14,%RCX,1),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0xc0(%R11,%RCX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD 0xc0(%RCX,%RSI,1),%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD 0xc0(%RBX,%RCX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM13,%ZMM4,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM1,0xc0(%R12,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 43642a <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x420a> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
