| Loop Id: 185 | Module: exec | Source: calc_dt_kernel.f90:99-129 | Coverage: 3.37% |
|---|
| Loop Id: 185 | Module: exec | Source: calc_dt_kernel.f90:99-129 | Coverage: 3.37% |
|---|
0x43bd60 MOV -0x40(%RBP),%RDX [14] |
0x43bd64 VMOVSD (%RDX),%XMM4 [11] |
0x43bd68 VMINSD %XMM21,%XMM4,%XMM2 |
0x43bd6e LEA 0x1(%RAX),%RDX |
0x43bd72 VMINSD %XMM6,%XMM2,%XMM6 |
0x43bd76 VMINSD %XMM6,%XMM9,%XMM9 |
0x43bd7a CMP %RAX,-0x38(%RBP) [14] |
0x43bd7e JE 43be88 |
0x43bd84 MOV %RDX,%RAX |
0x43bd87 VMOVSD (%R13,%RAX,8),%XMM2 [9] |
0x43bd8e VMOVSD (%R14,%RAX,8),%XMM1 [12] |
0x43bd94 VMINSD (%R15,%RAX,8),%XMM17,%XMM23 [4] |
0x43bd9b VADDSD %XMM2,%XMM2,%XMM4 |
0x43bd9f VMOVSD %XMM3,%XMM3,%XMM2 |
0x43bda3 VMOVSD 0x8(%R8,%RAX,8),%XMM3 [10] |
0x43bdaa VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM0 [3] |
0x43bdb1 VMULSD %XMM13,%XMM23,%XMM24 |
0x43bdb7 VDIVSD (%R12,%RAX,8),%XMM4,%XMM6 [13] |
0x43bdbd VMOVSD (%RBX,%RAX,8),%XMM4 [8] |
0x43bdc2 VFMADD132SD %XMM1,%XMM6,%XMM1 |
0x43bdc7 VANDPD %XMM5,%XMM2,%XMM6 |
0x43bdcb VMULSD %XMM4,%XMM8,%XMM20 |
0x43bdd1 VMULSD 0x8(%RDI,%RAX,8),%XMM0,%XMM3 [1] |
0x43bdd7 VMULSD %XMM4,%XMM11,%XMM18 |
0x43bddd VMULSD %XMM4,%XMM10,%XMM22 |
0x43bde3 VSQRTSD %XMM1,%XMM1,%XMM1 |
0x43bde7 VADDSD %XMM4,%XMM4,%XMM4 |
0x43bdeb VMAXSD %XMM20,%XMM6,%XMM0 |
0x43bdf1 VANDPD %XMM5,%XMM3,%XMM6 |
0x43bdf5 VMAXSD %XMM1,%XMM8,%XMM1 |
0x43bdf9 VMAXSD %XMM6,%XMM0,%XMM0 |
0x43bdfd VMOVSD %XMM7,%XMM7,%XMM6 |
0x43be01 VMOVSD 0x8(%RSI,%RAX,8),%XMM7 [7] |
0x43be07 VDIVSD %XMM0,%XMM18,%XMM21 |
0x43be0d VADDSD %XMM7,%XMM6,%XMM0 |
0x43be11 VMOVSD %XMM12,%XMM12,%XMM6 |
0x43be15 VMOVSD 0x8(%RCX,%RAX,8),%XMM12 [15] |
0x43be1b VADDSD %XMM12,%XMM6,%XMM6 |
0x43be20 VMULSD (%R11,%RAX,8),%XMM0,%XMM0 [5] |
0x43be26 VMULSD (%R10,%RAX,8),%XMM6,%XMM6 [6] |
0x43be2c VSUBSD %XMM0,%XMM3,%XMM19 |
0x43be32 VANDPD %XMM5,%XMM0,%XMM0 |
0x43be36 VSUBSD %XMM2,%XMM6,%XMM2 |
0x43be3a VANDPD %XMM5,%XMM6,%XMM6 |
0x43be3e VMAXSD %XMM0,%XMM6,%XMM6 |
0x43be42 VADDSD %XMM19,%XMM2,%XMM2 |
0x43be48 VMAXSD %XMM20,%XMM6,%XMM0 |
0x43be4e VDIVSD %XMM4,%XMM2,%XMM2 |
0x43be52 VDIVSD %XMM0,%XMM22,%XMM6 |
0x43be58 VCOMISD %XMM2,%XMM14 |
0x43be5c VDIVSD %XMM1,%XMM24,%XMM0 |
0x43be62 VMINSD %XMM0,%XMM6,%XMM6 |
0x43be66 JBE 43bd60 |
0x43be6c VDIVSD %XMM2,%XMM16,%XMM1 |
0x43be72 MOV -0x48(%RBP),%RDX [14] |
0x43be76 VXORPD %XMM15,%XMM1,%XMM0 |
0x43be7b VMULSD (%RDX),%XMM0,%XMM4 [2] |
0x43be7f JMP 43bd68 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 99 - 129 |
-------------------------------------------------------------------------------- |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.89 |
| Bottlenecks | |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 26.50 |
| CQA cycles if no scalar integer | 26.50 |
| CQA cycles if FP arith vectorized | 13.25 |
| CQA cycles if fully vectorized | 13.25 |
| Front-end cycles | 10.08 |
| DIV/SQRT cycles | 14.00 |
| P0 cycles | 13.67 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.83 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.00 |
| P11 cycles | 26.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 28.30 - 27.59 |
| Stall cycles (UFS) | 17.51 - 16.79 |
| Nb insns | 54.50 |
| Nb uops | 54.50 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.91 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 7.50 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 5.50 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.55 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 9.36 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 24.27 |
| Vector-efficiency ratio all | 13.67 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.53 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.97 |
| Bottlenecks | P0, |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 28.50 |
| CQA cycles if no scalar integer | 28.50 |
| CQA cycles if FP arith vectorized | 14.25 |
| CQA cycles if fully vectorized | 14.25 |
| Front-end cycles | 10.33 |
| DIV/SQRT cycles | 14.50 |
| P0 cycles | 14.17 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 14.33 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.00 |
| P11 cycles | 28.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 30.42 - 29.52 |
| Stall cycles (UFS) | 19.38 - 18.48 |
| Nb insns | 56.00 |
| Nb uops | 56.00 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.88 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 6.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.21 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 10.20 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 26.32 |
| Vector-efficiency ratio all | 13.78 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.79 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.00 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.81 |
| Bottlenecks | P0, |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:99-129 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.50 |
| CQA cycles if no scalar integer | 24.50 |
| CQA cycles if FP arith vectorized | 12.25 |
| CQA cycles if fully vectorized | 12.25 |
| Front-end cycles | 9.83 |
| DIV/SQRT cycles | 13.50 |
| P0 cycles | 13.17 |
| P1 cycles | 5.00 |
| P2 cycles | 5.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.33 |
| P5 cycles | 2.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 5.00 |
| P11 cycles | 24.50 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 26.19 - 25.65 |
| Stall cycles (UFS) | 15.64 - 15.10 |
| Nb insns | 53.00 |
| Nb uops | 53.00 |
| Nb loads | 15.00 |
| Nb stores | 0.00 |
| Nb stack references | 2.00 |
| FLOP/cycle | 0.94 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 7.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 5.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 1.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 4.90 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 120.00 |
| Bytes stored | 0.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 12.00 |
| Vectorization ratio all | 8.51 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 0.00 |
| Vectorization ratio other | 22.22 |
| Vector-efficiency ratio all | 13.56 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 12.50 |
| Vector-efficiency ratio other | 15.28 |
| Path / |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 54.50 |
| nb uops | 54.50 |
| loop length | 276 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 24 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.07 |
| micro-operation queue | 10.08 cycles |
| front end | 10.08 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.00 | 13.67 | 5.00 | 5.00 | 0.00 | 13.83 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| cycles | 14.00 | 13.67 | 5.00 | 5.00 | 0.00 | 13.83 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| Cycles executing div or sqrt instructions | 26.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 28.30-27.59 |
| Stall cycles | 17.51-16.79 |
| PRF_FLOAT full (events) | 19.55-18.62 |
| Front-end | 10.08 |
| Dispatch | 14.00 |
| DIV/SQRT | 26.50 |
| Data deps. | 4.00 |
| Overall L1 | 26.50 |
| all | 9% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 24% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 56 |
| nb uops | 56 |
| loop length | 284 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 25 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 10.33 cycles |
| front end | 10.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.50 | 14.17 | 5.00 | 5.00 | 0.00 | 14.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| cycles | 14.50 | 14.17 | 5.00 | 5.00 | 0.00 | 14.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| Cycles executing div or sqrt instructions | 28.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 30.42-29.52 |
| Stall cycles | 19.38-18.48 |
| PRF_FLOAT full (events) | 20.71-19.81 |
| Front-end | 10.33 |
| Dispatch | 14.50 |
| DIV/SQRT | 28.50 |
| Data deps. | 4.00 |
| Overall L1 | 28.50 |
| all | 10% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 26% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMINSD %XMM21,%XMM4,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMINSD %XMM6,%XMM2,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD %XMM6,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JE 43be88 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD (%R13,%RAX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R14,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMINSD (%R15,%RAX,8),%XMM17,%XMM23 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM2,%XMM2,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD %XMM3,%XMM3,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%R8,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMULSD %XMM13,%XMM23,%XMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD (%R12,%RAX,8),%XMM4,%XMM6 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VMOVSD (%RBX,%RAX,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132SD %XMM1,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VANDPD %XMM5,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMULSD %XMM4,%XMM8,%XMM20 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD 0x8(%RDI,%RAX,8),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM4,%XMM11,%XMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM4,%XMM10,%XMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSQRTSD %XMM1,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VADDSD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM20,%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VANDPD %XMM5,%XMM3,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM1,%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM6,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,%XMM7,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%RSI,%RAX,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VDIVSD %XMM0,%XMM18,%XMM21 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VADDSD %XMM7,%XMM6,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD %XMM12,%XMM12,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%RCX,%RAX,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM12,%XMM6,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%R11,%RAX,8),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD (%R10,%RAX,8),%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBSD %XMM0,%XMM3,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM5,%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VSUBSD %XMM2,%XMM6,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM5,%XMM6,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM0,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM19,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM20,%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM4,%XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VDIVSD %XMM0,%XMM22,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VCOMISD %XMM2,%XMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVSD %XMM1,%XMM24,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMINSD %XMM0,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JBE 43bd60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VDIVSD %XMM2,%XMM16,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VXORPD %XMM15,%XMM1,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VMULSD (%RDX),%XMM0,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| JMP 43bd68 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3c8> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:99-129 |
| Module | exec |
| nb instructions | 53 |
| nb uops | 53 |
| loop length | 268 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 23 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| ADD-SUB / MUL ratio | 1.14 |
| micro-operation queue | 9.83 cycles |
| front end | 9.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.50 | 13.17 | 5.00 | 5.00 | 0.00 | 13.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| cycles | 13.50 | 13.17 | 5.00 | 5.00 | 0.00 | 13.33 | 2.00 | 0.00 | 0.00 | 0.00 | 1.00 | 5.00 |
| Cycles executing div or sqrt instructions | 24.50 |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 26.19-25.65 |
| Stall cycles | 15.64-15.10 |
| PRF_FLOAT full (events) | 18.40-17.42 |
| Front-end | 9.83 |
| Dispatch | 13.50 |
| DIV/SQRT | 24.50 |
| Data deps. | 4.00 |
| Overall L1 | 24.50 |
| all | 8% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | 0% |
| div/sqrt | 0% |
| other | 22% |
| all | 13% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | 12% |
| div/sqrt | 12% |
| other | 15% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%RDX),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMINSD %XMM21,%XMM4,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMINSD %XMM6,%XMM2,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINSD %XMM6,%XMM9,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %RAX,-0x38(%RBP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JE 43be88 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x4e8> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| MOV %RDX,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD (%R13,%RAX,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R14,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMINSD (%R15,%RAX,8),%XMM17,%XMM23 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM2,%XMM2,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD %XMM3,%XMM3,%XMM2 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%R8,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD 0x8(%R9,%RAX,8),%XMM3,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMULSD %XMM13,%XMM23,%XMM24 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD (%R12,%RAX,8),%XMM4,%XMM6 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VMOVSD (%RBX,%RAX,8),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132SD %XMM1,%XMM6,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VANDPD %XMM5,%XMM2,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMULSD %XMM4,%XMM8,%XMM20 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD 0x8(%RDI,%RAX,8),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM4,%XMM11,%XMM18 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM4,%XMM10,%XMM22 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSQRTSD %XMM1,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VADDSD %XMM4,%XMM4,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM20,%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VANDPD %XMM5,%XMM3,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM1,%XMM8,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMAXSD %XMM6,%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD %XMM7,%XMM7,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%RSI,%RAX,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VDIVSD %XMM0,%XMM18,%XMM21 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VADDSD %XMM7,%XMM6,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD %XMM12,%XMM12,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD 0x8(%RCX,%RAX,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM12,%XMM6,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%R11,%RAX,8),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD (%R10,%RAX,8),%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBSD %XMM0,%XMM3,%XMM19 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM5,%XMM0,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VSUBSD %XMM2,%XMM6,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %XMM5,%XMM6,%XMM6 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMAXSD %XMM0,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM19,%XMM2,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMAXSD %XMM20,%XMM6,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM4,%XMM2,%XMM2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VDIVSD %XMM0,%XMM22,%XMM6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VCOMISD %XMM2,%XMM14 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVSD %XMM1,%XMM24,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VMINSD %XMM0,%XMM6,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| JBE 43bd60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x3c0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
