| Loop Id: 134 | Module: exec | Source: advec_cell_kernel.f90:255-261 | Coverage: 3.53% |
|---|
| Loop Id: 134 | Module: exec | Source: advec_cell_kernel.f90:255-261 | Coverage: 3.53% |
|---|
0x426780 VMOVUPD (%RSI,%RAX,8),%YMM0 [9] |
0x426785 VMULPD (%R14,%RAX,8),%YMM0,%YMM1 [6] |
0x42678b VADDPD (%R15,%RAX,8),%YMM1,%YMM2 [7] |
0x426791 VSUBPD (%R11,%RAX,8),%YMM2,%YMM2 [3] |
0x426797 VMOVUPD (%RDI,%RAX,8),%YMM3 [4] |
0x42679c VFMADD213PD (%R9,%RAX,8),%YMM1,%YMM3 [1] |
0x4267a2 VSUBPD (%R13,%RAX,8),%YMM3,%YMM1 [8] |
0x4267a9 VDIVPD %YMM2,%YMM1,%YMM1 |
0x4267ad VADDPD (%RDX,%RAX,8),%YMM0,%YMM0 [2] |
0x4267b2 VSUBPD (%R8,%RAX,8),%YMM0,%YMM0 [5] |
0x4267b8 VDIVPD %YMM0,%YMM2,%YMM0 |
0x4267bc VMOVUPD %YMM0,(%R14,%RAX,8) [6] |
0x4267c2 VMOVUPD %YMM1,(%RDI,%RAX,8) [4] |
0x4267c7 ADD $0x4,%RAX |
0x4267cb CMP %RCX,%RAX |
0x4267ce JB 426780 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 255 - 261 |
-------------------------------------------------------------------------------- |
255: DO j=x_min,x_max |
256: pre_mass_s=density1(j,k)*pre_vol(j,k) |
257: post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1) |
258: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s |
259: advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1) |
260: density1(j,k)=post_mass_s/advec_vol_s |
261: energy1(j,k)=post_ener_s |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.36 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:255-261 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 3.67 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 3.50 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 3.00 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 16.28 - 16.30 |
| Stall cycles (UFS) | 11.84 - 11.86 |
| Nb insns | 16.00 |
| Nb uops | 15.00 |
| Nb loads | 9.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.50 |
| Nb FLOP add-sub | 20.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 288.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 9.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.36 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:255-261 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 16.00 |
| CQA cycles if fully vectorized | 16.00 |
| Front-end cycles | 3.67 |
| DIV/SQRT cycles | 2.50 |
| P0 cycles | 3.50 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 3.00 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 16.28 - 16.30 |
| Stall cycles (UFS) | 11.84 - 11.86 |
| Nb insns | 16.00 |
| Nb uops | 15.00 |
| Nb loads | 9.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.50 |
| Nb FLOP add-sub | 20.00 |
| Nb FLOP mul | 4.00 |
| Nb FLOP fma | 4.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 288.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 9.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | 50.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:255-261 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 15 |
| loop length | 80 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 4 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 3.67 cycles |
| front end | 3.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 3.50 | 3.00 | 3.00 | 1.00 | 3.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| cycles | 2.50 | 3.50 | 3.00 | 3.00 | 1.00 | 3.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 16.28-16.30 |
| Stall cycles | 11.84-11.86 |
| LB full (events) | 13.43-13.46 |
| Front-end | 3.67 |
| Dispatch | 3.50 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RSI,%RAX,8),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD (%R14,%RAX,8),%YMM0,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD (%R15,%RAX,8),%YMM1,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R11,%RAX,8),%YMM2,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD (%RDI,%RAX,8),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMADD213PD (%R9,%RAX,8),%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBPD (%R13,%RAX,8),%YMM3,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD %YMM2,%YMM1,%YMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
| VADDPD (%RDX,%RAX,8),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R8,%RAX,8),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD %YMM0,%YMM2,%YMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
| VMOVUPD %YMM0,(%R14,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD %YMM1,(%RDI,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x4,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 426780 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0xaa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:255-261 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 15 |
| loop length | 80 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 4 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 3.67 cycles |
| front end | 3.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.50 | 3.50 | 3.00 | 3.00 | 1.00 | 3.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| cycles | 2.50 | 3.50 | 3.00 | 3.00 | 1.00 | 3.00 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 16.28-16.30 |
| Stall cycles | 11.84-11.86 |
| LB full (events) | 13.43-13.46 |
| Front-end | 3.67 |
| Dispatch | 3.50 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 16.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | 50% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RSI,%RAX,8),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD (%R14,%RAX,8),%YMM0,%YMM1 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD (%R15,%RAX,8),%YMM1,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R11,%RAX,8),%YMM2,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD (%RDI,%RAX,8),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMADD213PD (%R9,%RAX,8),%YMM1,%YMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBPD (%R13,%RAX,8),%YMM3,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD %YMM2,%YMM1,%YMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
| VADDPD (%RDX,%RAX,8),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD (%R8,%RAX,8),%YMM0,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VDIVPD %YMM0,%YMM2,%YMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 8 |
| VMOVUPD %YMM0,(%R14,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD %YMM1,(%RDI,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x4,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RCX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 426780 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0xaa0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
