| Loop Id: 95 | Module: exec | Source: accelerate_kernel.f90:67-76 | Coverage: 5.54% |
|---|
| Loop Id: 95 | Module: exec | Source: accelerate_kernel.f90:67-76 | Coverage: 5.54% |
|---|
0x42a2a0 MOV 0x310(%RSP),%RBX [24] |
0x42a2a8 MOV 0x2b0(%RSP),%R12 [24] |
0x42a2b0 VMOVUPD (%R15,%RAX,1),%ZMM14 [18] |
0x42a2b7 VMOVUPD (%RBX,%RAX,1),%ZMM0 [15] |
0x42a2be MOV 0x328(%RSP),%RBX [24] |
0x42a2c6 VMULPD (%R12,%RAX,1),%ZMM0,%ZMM8 [4] |
0x42a2cd VMOVUPD (%RBX,%RAX,1),%ZMM1 [13] |
0x42a2d4 MOV 0x2b8(%RSP),%R12 [24] |
0x42a2dc MOV 0x2c0(%RSP),%RBX [24] |
0x42a2e4 VSUBPD (%R11,%RAX,1),%ZMM14,%ZMM0 [6] |
0x42a2eb VMOVUPD (%RBX,%RAX,1),%ZMM9 [21] |
0x42a2f2 MOV 0x300(%RSP),%RBX [24] |
0x42a2fa VFMADD231PD (%R12,%RAX,1),%ZMM1,%ZMM8 [12] |
0x42a301 MOV 0x2a8(%RSP),%R12 [24] |
0x42a309 VMOVUPD (%RBX,%RAX,1),%ZMM10 [3] |
0x42a310 MOV 0x330(%RSP),%RBX [24] |
0x42a318 VMULPD (%R12,%RAX,1),%ZMM9,%ZMM11 [23] |
0x42a31f MOV 0x308(%RSP),%R12 [24] |
0x42a327 VFMADD231PD (%R12,%RAX,1),%ZMM10,%ZMM11 [10] |
0x42a32e MOV 0x2c8(%RSP),%R12 [24] |
0x42a336 VADDPD %ZMM11,%ZMM8,%ZMM12 |
0x42a33c VMOVUPD (%R9,%RAX,1),%ZMM8 [1] |
0x42a343 VSUBPD (%R8,%RAX,1),%ZMM8,%ZMM1 [5] |
0x42a34a VMULPD %ZMM5,%ZMM12,%ZMM13 |
0x42a350 VMULPD (%R10,%RAX,1),%ZMM1,%ZMM9 [20] |
0x42a357 VDIVPD %ZMM13,%ZMM2,%ZMM15 |
0x42a35d VFMADD132PD (%RBX,%RAX,1),%ZMM9,%ZMM0 [22] |
0x42a364 MOV 0x338(%RSP),%RBX [24] |
0x42a36c VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM0 [25] |
0x42a373 VMOVUPD %ZMM0,(%RDX,%RAX,1) [19] |
0x42a37a VMOVUPD (%R11,%RAX,1),%ZMM12 [6] |
0x42a381 VMOVUPD (%R15,%RAX,1),%ZMM11 [18] |
0x42a388 VSUBPD (%R8,%RAX,1),%ZMM12,%ZMM13 [5] |
0x42a38f VSUBPD (%R9,%RAX,1),%ZMM11,%ZMM10 [1] |
0x42a396 VMULPD (%RDI,%RAX,1),%ZMM13,%ZMM14 [14] |
0x42a39d VFMADD132PD (%RBX,%RAX,1),%ZMM14,%ZMM10 [2] |
0x42a3a4 MOV 0x2d0(%RSP),%R12 [24] |
0x42a3ac MOV 0x330(%RSP),%RBX [24] |
0x42a3b4 VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM10 [8] |
0x42a3bb MOV 0x2a0(%RSP),%R12 [24] |
0x42a3c3 VMOVUPD %ZMM10,(%R14,%RAX,1) [9] |
0x42a3ca VMOVUPD (%RCX,%RAX,1),%ZMM8 [11] |
0x42a3d1 VMOVUPD (%R13,%RAX,1),%ZMM0 [7] |
0x42a3d9 VSUBPD (%R12,%RAX,1),%ZMM8,%ZMM9 [16] |
0x42a3e0 VSUBPD (%RSI,%RAX,1),%ZMM0,%ZMM1 [17] |
0x42a3e7 VMULPD (%R10,%RAX,1),%ZMM9,%ZMM11 [20] |
0x42a3ee VFMADD132PD (%RBX,%RAX,1),%ZMM11,%ZMM1 [22] |
0x42a3f5 MOV 0x338(%RSP),%RBX [24] |
0x42a3fd VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM1 [19] |
0x42a404 VMOVUPD %ZMM1,(%RDX,%RAX,1) [19] |
0x42a40b VMOVUPD (%RSI,%RAX,1),%ZMM13 [17] |
0x42a412 VMOVUPD (%R13,%RAX,1),%ZMM10 [7] |
0x42a41a VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 [16] |
0x42a421 VSUBPD (%RCX,%RAX,1),%ZMM10,%ZMM12 [11] |
0x42a428 VMULPD (%RDI,%RAX,1),%ZMM14,%ZMM0 [14] |
0x42a42f VFMADD132PD (%RBX,%RAX,1),%ZMM0,%ZMM12 [2] |
0x42a436 VFNMADD213PD (%R14,%RAX,1),%ZMM12,%ZMM15 [9] |
0x42a43d VMOVUPD %ZMM15,(%R14,%RAX,1) [9] |
0x42a444 ADD $0x40,%RAX |
0x42a448 CMP %RAX,0x298(%RSP) [24] |
0x42a450 JNE 42a2a0 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 67 - 76 |
-------------------------------------------------------------------------------- |
67: *0.25_8) |
68: |
69: xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j ,k )*(pressure(j ,k )-pressure(j-1,k )) & |
70: +xarea(j ,k-1)*(pressure(j ,k-1)-pressure(j-1,k-1))) |
71: yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j ,k )*(pressure(j ,k )-pressure(j ,k-1)) & |
72: +yarea(j-1,k )*(pressure(j-1,k )-pressure(j-1,k-1))) |
73: xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j ,k )*(viscosity(j ,k )-viscosity(j-1,k )) & |
74: +xarea(j ,k-1)*(viscosity(j ,k-1)-viscosity(j-1,k-1))) |
75: yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j ,k )*(viscosity(j ,k )-viscosity(j ,k-1)) & |
76: +yarea(j-1,k )*(viscosity(j-1,k )-viscosity(j-1,k-1))) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.08 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P2, P3, P11, |
| Function | accelerate_kernel._omp_fn.0 |
| Source | accelerate_kernel.f90:67-76 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 17.33 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 17.33 |
| CQA cycles if fully vectorized | 17.33 |
| Front-end cycles | 14.33 |
| DIV/SQRT cycles | 14.50 |
| P0 cycles | 13.00 |
| P1 cycles | 17.33 |
| P2 cycles | 17.33 |
| P3 cycles | 2.00 |
| P4 cycles | 14.50 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 17.33 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 18.99 - 19.06 |
| Stall cycles (UFS) | 4.26 - 4.28 |
| Nb insns | 61.00 |
| Nb uops | 62.00 |
| Nb loads | 52.00 |
| Nb stores | 4.00 |
| Nb stack references | 14.00 |
| FLOP/cycle | 17.08 |
| Nb FLOP add-sub | 72.00 |
| Nb FLOP mul | 56.00 |
| Nb FLOP fma | 80.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 155.08 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 2432.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 11.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.08 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P2, P3, P11, |
| Function | accelerate_kernel._omp_fn.0 |
| Source | accelerate_kernel.f90:67-76 |
| Source loop unroll info | unrolled by 8 |
| Source loop unroll confidence level | high |
| Unroll/vectorization loop type | main |
| Unroll factor | 8 |
| CQA cycles | 17.33 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 17.33 |
| CQA cycles if fully vectorized | 17.33 |
| Front-end cycles | 14.33 |
| DIV/SQRT cycles | 14.50 |
| P0 cycles | 13.00 |
| P1 cycles | 17.33 |
| P2 cycles | 17.33 |
| P3 cycles | 2.00 |
| P4 cycles | 14.50 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 17.33 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 18.99 - 19.06 |
| Stall cycles (UFS) | 4.26 - 4.28 |
| Nb insns | 61.00 |
| Nb uops | 62.00 |
| Nb loads | 52.00 |
| Nb stores | 4.00 |
| Nb stack references | 14.00 |
| FLOP/cycle | 17.08 |
| Nb FLOP add-sub | 72.00 |
| Nb FLOP mul | 56.00 |
| Nb FLOP fma | 80.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 155.08 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 2432.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 11.00 |
| Stride unknown | 2.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | accelerate_kernel._omp_fn.0 |
| Source file and lines | accelerate_kernel.f90:67-76 |
| Module | exec |
| nb instructions | 61 |
| nb uops | 62 |
| loop length | 438 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 12 |
| nb stack references | 14 |
| ADD-SUB / MUL ratio | 1.29 |
| micro-operation queue | 14.33 cycles |
| front end | 14.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.50 | 0.00 | 17.33 | 17.33 | 2.00 | 14.50 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 17.33 |
| cycles | 14.50 | 13.00 | 17.33 | 17.33 | 2.00 | 14.50 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 17.33 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 18.99-19.06 |
| Stall cycles | 4.26-4.28 |
| LM full (events) | 10.24-10.30 |
| Front-end | 14.33 |
| Dispatch | 17.33 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 17.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x310(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x2b0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%R15,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x328(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R12,%RAX,1),%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x2b8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x2c0(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSUBPD (%R11,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RBX,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x300(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231PD (%R12,%RAX,1),%ZMM1,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2a8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RBX,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x330(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R12,%RAX,1),%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x308(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231PD (%R12,%RAX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2c8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %ZMM11,%ZMM8,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R9,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R8,%RAX,1),%ZMM8,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD %ZMM5,%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD (%R10,%RAX,1),%ZMM1,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VDIVPD %ZMM13,%ZMM2,%ZMM15 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM9,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x338(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM0,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%R11,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R15,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R8,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%R9,%RAX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%RDI,%RAX,1),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM14,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2d0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x330(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2a0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM10,(%R14,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R12,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RSI,%RAX,1),%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%R10,%RAX,1),%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM11,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x338(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM1,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%RSI,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RCX,%RAX,1),%ZMM10,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%RDI,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM0,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFNMADD213PD (%R14,%RAX,1),%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM15,(%R14,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RAX,0x298(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 42a2a0 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x7d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | accelerate_kernel._omp_fn.0 |
| Source file and lines | accelerate_kernel.f90:67-76 |
| Module | exec |
| nb instructions | 61 |
| nb uops | 62 |
| loop length | 438 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 12 |
| nb stack references | 14 |
| ADD-SUB / MUL ratio | 1.29 |
| micro-operation queue | 14.33 cycles |
| front end | 14.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.50 | 0.00 | 17.33 | 17.33 | 2.00 | 14.50 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 17.33 |
| cycles | 14.50 | 13.00 | 17.33 | 17.33 | 2.00 | 14.50 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 17.33 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 18.99-19.06 |
| Stall cycles | 4.26-4.28 |
| LM full (events) | 10.24-10.30 |
| Front-end | 14.33 |
| Dispatch | 17.33 |
| DIV/SQRT | 16.00 |
| Data deps. | 1.00 |
| Overall L1 | 17.33 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x310(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x2b0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%R15,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x328(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R12,%RAX,1),%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD (%RBX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x2b8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x2c0(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSUBPD (%R11,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RBX,%RAX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x300(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231PD (%R12,%RAX,1),%ZMM1,%ZMM8 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2a8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RBX,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x330(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R12,%RAX,1),%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x308(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231PD (%R12,%RAX,1),%ZMM10,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2c8(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %ZMM11,%ZMM8,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R9,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R8,%RAX,1),%ZMM8,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD %ZMM5,%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD (%R10,%RAX,1),%ZMM1,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VDIVPD %ZMM13,%ZMM2,%ZMM15 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM9,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x338(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM0,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%R11,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R15,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R8,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%R9,%RAX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%RDI,%RAX,1),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM14,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2d0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x330(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%R12,%RAX,1),%ZMM15,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x2a0(%RSP),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD %ZMM10,(%R14,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%RCX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R12,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RSI,%RAX,1),%ZMM0,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%R10,%RAX,1),%ZMM9,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM11,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x338(%RSP),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM1,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%RSI,%RAX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R13,%RAX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%R12,%RAX,1),%ZMM13,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RCX,%RAX,1),%ZMM10,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD (%RDI,%RAX,1),%ZMM14,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM0,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFNMADD213PD (%R14,%RAX,1),%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM15,(%R14,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RAX,0x298(%RSP) | 1 | 0.20 | 0.20 | 0.33 | 0.33 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.33 | 1 | 0.33 |
| JNE 42a2a0 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x7d0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
