| Loop Id: 152 | Module: exec | Source: advec_mom_kernel.f90:106-107 | Coverage: 2.6% |
|---|
| Loop Id: 152 | Module: exec | Source: advec_mom_kernel.f90:106-107 | Coverage: 2.6% |
|---|
0x435e69 VMOVUPD (%R9,%RAX,1),%ZMM15 [3] |
0x435e70 VMOVUPD %ZMM15,(%R8,%RAX,1) [1] |
0x435e77 VADDPD (%RDI,%RAX,1),%ZMM15,%ZMM1 [2] |
0x435e7e VSUBPD (%RSI,%RAX,1),%ZMM1,%ZMM0 [4] |
0x435e85 VMOVUPD %ZMM0,(%RCX,%RAX,1) [5] |
0x435e8c VMOVUPD 0x40(%R9,%RAX,1),%ZMM2 [3] |
0x435e94 VMOVUPD %ZMM2,0x40(%R8,%RAX,1) [1] |
0x435e9c VADDPD 0x40(%RDI,%RAX,1),%ZMM2,%ZMM3 [2] |
0x435ea4 VSUBPD 0x40(%RSI,%RAX,1),%ZMM3,%ZMM4 [4] |
0x435eac VMOVUPD %ZMM4,0x40(%RCX,%RAX,1) [5] |
0x435eb4 VMOVUPD 0x80(%R9,%RAX,1),%ZMM5 [3] |
0x435ebc VMOVUPD %ZMM5,0x80(%R8,%RAX,1) [1] |
0x435ec4 VADDPD 0x80(%RDI,%RAX,1),%ZMM5,%ZMM6 [2] |
0x435ecc VSUBPD 0x80(%RSI,%RAX,1),%ZMM6,%ZMM7 [4] |
0x435ed4 VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) [5] |
0x435edc VMOVUPD 0xc0(%R9,%RAX,1),%ZMM8 [3] |
0x435ee4 VMOVUPD %ZMM8,0xc0(%R8,%RAX,1) [1] |
0x435eec VADDPD 0xc0(%RDI,%RAX,1),%ZMM8,%ZMM9 [2] |
0x435ef4 VSUBPD 0xc0(%RSI,%RAX,1),%ZMM9,%ZMM10 [4] |
0x435efc VMOVUPD %ZMM10,0xc0(%RCX,%RAX,1) [5] |
0x435f04 VMOVUPD 0x100(%R9,%RAX,1),%ZMM11 [3] |
0x435f0c VMOVUPD %ZMM11,0x100(%R8,%RAX,1) [1] |
0x435f14 VADDPD 0x100(%RDI,%RAX,1),%ZMM11,%ZMM12 [2] |
0x435f1c VSUBPD 0x100(%RSI,%RAX,1),%ZMM12,%ZMM13 [4] |
0x435f24 VMOVUPD %ZMM13,0x100(%RCX,%RAX,1) [5] |
0x435f2c VMOVUPD 0x140(%R9,%RAX,1),%ZMM14 [3] |
0x435f34 VMOVUPD %ZMM14,0x140(%R8,%RAX,1) [1] |
0x435f3c VADDPD 0x140(%RDI,%RAX,1),%ZMM14,%ZMM15 [2] |
0x435f44 VSUBPD 0x140(%RSI,%RAX,1),%ZMM15,%ZMM1 [4] |
0x435f4c VMOVUPD %ZMM1,0x140(%RCX,%RAX,1) [5] |
0x435f54 VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 [3] |
0x435f5c VMOVUPD %ZMM0,0x180(%R8,%RAX,1) [1] |
0x435f64 VADDPD 0x180(%RDI,%RAX,1),%ZMM0,%ZMM2 [2] |
0x435f6c MOV 0x1f0(%RSP),%RDX [6] |
0x435f74 VSUBPD 0x180(%RSI,%RAX,1),%ZMM2,%ZMM3 [4] |
0x435f7c VMOVUPD %ZMM3,0x180(%RCX,%RAX,1) [5] |
0x435f84 VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM4 [3] |
0x435f8c VMOVUPD %ZMM4,0x1c0(%R8,%RAX,1) [1] |
0x435f94 VADDPD 0x1c0(%RDI,%RAX,1),%ZMM4,%ZMM5 [2] |
0x435f9c VSUBPD 0x1c0(%RSI,%RAX,1),%ZMM5,%ZMM6 [4] |
0x435fa4 VMOVUPD %ZMM6,0x1c0(%RCX,%RAX,1) [5] |
0x435fac ADD $0x200,%RAX |
0x435fb2 CMP %RDX,%RAX |
0x435fb5 JNE 435e69 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 106 - 107 |
-------------------------------------------------------------------------------- |
106: post_vol(j,k)=volume(j,k) |
107: pre_vol(j,k)=post_vol(j,k)+vol_flux_y(j ,k+1)-vol_flux_y(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.18 |
| Bottlenecks | micro-operation queue, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:106-107 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 9.83 |
| CQA cycles if no scalar integer | 9.83 |
| CQA cycles if FP arith vectorized | 9.83 |
| CQA cycles if fully vectorized | 9.83 |
| Front-end cycles | 9.83 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 8.33 |
| P2 cycles | 8.33 |
| P3 cycles | 8.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 8.00 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 0.40 |
| P10 cycles | 8.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 10.02 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 44.00 |
| Nb uops | 43.00 |
| Nb loads | 25.00 |
| Nb stores | 16.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 13.02 |
| Nb FLOP add-sub | 128.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 261.15 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1544.00 |
| Bytes stored | 1024.00 |
| Stride 0 | 1.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.18 |
| Bottlenecks | micro-operation queue, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:106-107 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 9.83 |
| CQA cycles if no scalar integer | 9.83 |
| CQA cycles if FP arith vectorized | 9.83 |
| CQA cycles if fully vectorized | 9.83 |
| Front-end cycles | 9.83 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 8.33 |
| P2 cycles | 8.33 |
| P3 cycles | 8.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 8.00 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 0.40 |
| P10 cycles | 8.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 10.02 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 44.00 |
| Nb uops | 43.00 |
| Nb loads | 25.00 |
| Nb stores | 16.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 13.02 |
| Nb FLOP add-sub | 128.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 261.15 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1544.00 |
| Bytes stored | 1024.00 |
| Stride 0 | 1.00 |
| Stride 1 | 5.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:106-107 |
| Module | exec |
| nb instructions | 44 |
| nb uops | 43 |
| loop length | 338 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 1 |
| micro-operation queue | 9.83 cycles |
| front end | 9.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.60 | 8.33 | 8.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.33 |
| cycles | 8.00 | 8.00 | 8.33 | 8.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 10.02 |
| Stall cycles | 0.00 |
| Front-end | 9.83 |
| Dispatch | 8.33 |
| Data deps. | 1.00 |
| Overall L1 | 9.83 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R9,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM15,(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD (%RDI,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RSI,%RAX,1),%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM0,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R9,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x40(%RDI,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x40(%RSI,%RAX,1),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM4,0x40(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x80(%R9,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM5,0x80(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x80(%RDI,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x80(%RSI,%RAX,1),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0xc0(%R9,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM8,0xc0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0xc0(%RDI,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0xc0(%RSI,%RAX,1),%ZMM9,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM10,0xc0(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x100(%R9,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM11,0x100(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x100(%RDI,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x100(%RSI,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM13,0x100(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x140(%R9,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM14,0x140(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x140(%RDI,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x140(%RSI,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM1,0x140(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM0,0x180(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x180(%RDI,%RAX,1),%ZMM0,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x1f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSUBPD 0x180(%RSI,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM3,0x180(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM4,0x1c0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x1c0(%RDI,%RAX,1),%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x1c0(%RSI,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM6,0x1c0(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 435e69 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3c49> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:106-107 |
| Module | exec |
| nb instructions | 44 |
| nb uops | 43 |
| loop length | 338 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 16 |
| nb stack references | 1 |
| micro-operation queue | 9.83 cycles |
| front end | 9.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.60 | 8.33 | 8.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.33 |
| cycles | 8.00 | 8.00 | 8.33 | 8.33 | 8.00 | 8.00 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 8.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 10.02 |
| Stall cycles | 0.00 |
| Front-end | 9.83 |
| Dispatch | 8.33 |
| Data deps. | 1.00 |
| Overall L1 | 9.83 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R9,%RAX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM15,(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD (%RDI,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RSI,%RAX,1),%ZMM1,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM0,(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R9,%RAX,1),%ZMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM2,0x40(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x40(%RDI,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x40(%RSI,%RAX,1),%ZMM3,%ZMM4 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM4,0x40(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x80(%R9,%RAX,1),%ZMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM5,0x80(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x80(%RDI,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x80(%RSI,%RAX,1),%ZMM6,%ZMM7 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM7,0x80(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0xc0(%R9,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM8,0xc0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0xc0(%RDI,%RAX,1),%ZMM8,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0xc0(%RSI,%RAX,1),%ZMM9,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM10,0xc0(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x100(%R9,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM11,0x100(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x100(%RDI,%RAX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x100(%RSI,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM13,0x100(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x140(%R9,%RAX,1),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM14,0x140(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x140(%RDI,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x140(%RSI,%RAX,1),%ZMM15,%ZMM1 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM1,0x140(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x180(%R9,%RAX,1),%ZMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM0,0x180(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x180(%RDI,%RAX,1),%ZMM0,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x1f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VSUBPD 0x180(%RSI,%RAX,1),%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM3,0x180(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x1c0(%R9,%RAX,1),%ZMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD %ZMM4,0x1c0(%R8,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VADDPD 0x1c0(%RDI,%RAX,1),%ZMM4,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD 0x1c0(%RSI,%RAX,1),%ZMM5,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD %ZMM6,0x1c0(%RCX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x200,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 435e69 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x3c49> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
