| Loop Id: 277 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 3.88% |
|---|
| Loop Id: 277 | Module: exec | Source: advec_mom_kernel.f90:81-241 [...] | Coverage: 3.88% |
|---|
0x43a480 VCMPPD $0x1,%ZMM30,%ZMM12,%K1 |
0x43a487 VMOVAPD %ZMM3,%ZMM2{%K1}{z} |
0x43a48d VSUBPD %ZMM29,%ZMM11,%ZMM3 |
0x43a493 VFMADD213PD %ZMM28,%ZMM2,%ZMM3 |
0x43a499 VMULPD %ZMM27,%ZMM3,%ZMM2 |
0x43a49f VMOVUPD %ZMM2,(%R14,%R11,8) [5] |
0x43a4a6 ADD $0x8,%R11 |
0x43a4aa CMP %R12,%R11 |
0x43a4ad JA 43a6c0 |
0x43a4b3 VMOVUPD (%R15,%R11,8),%ZMM27 [3] |
0x43a4ba VFPCLASSPD $0x50,%ZMM27,%K1 |
0x43a4c1 VMOVDQA64 %YMM25,%YMM3 |
0x43a4c7 VPBROADCASTD %ECX,%YMM3{%K1} |
0x43a4cd VPMOVSXDQ %YMM3,%ZMM3 |
0x43a4d3 VPSUBQ %ZMM5,%ZMM3,%ZMM3 |
0x43a4d9 VPXOR %XMM7,%XMM7,%XMM7 |
0x43a4dd VPMULLQ %ZMM3,%ZMM0,%ZMM7 |
0x43a4e3 LEA (%RDX,%R11,1),%RSI |
0x43a4e7 VMOVQ %RSI,%XMM28 |
0x43a4ed VPSUBQ %XMM26,%XMM28,%XMM28 |
0x43a4f3 VPSLLQ $0x3,%XMM28,%XMM28 |
0x43a4fa VPBROADCASTQ %XMM28,%ZMM28 |
0x43a500 VPADDQ %ZMM9,%ZMM28,%ZMM28 |
0x43a506 VPADDQ %ZMM28,%ZMM6,%ZMM29 |
0x43a50c VPADDQ %ZMM7,%ZMM29,%ZMM7 |
0x43a512 VPXORD %XMM29,%XMM29,%XMM29 |
0x43a518 KXNORW %K0,%K0,%K2 |
0x43a51c VGATHERQPD (,%ZMM7,1),%ZMM29{%K2} [4] |
0x43a527 VPMULLQ %ZMM3,%ZMM1,%ZMM3 |
0x43a52d VPADDQ %ZMM28,%ZMM10,%ZMM7 |
0x43a533 VPADDQ %ZMM3,%ZMM7,%ZMM3 |
0x43a539 VPXORD %XMM28,%XMM28,%XMM28 |
0x43a53f KXNORW %K0,%K0,%K2 |
0x43a543 VGATHERQPD (,%ZMM3,1),%ZMM28{%K2} [2] |
0x43a54e VMOVDQA64 %YMM23,%YMM3 |
0x43a554 VPBROADCASTD %R9D,%YMM3{%K1} |
0x43a55a VMOVDQA64 %YMM24,%YMM30 |
0x43a560 VPMOVSXDQ %YMM3,%ZMM3 |
0x43a566 VPSUBQ %ZMM5,%ZMM3,%ZMM3 |
0x43a56c VPMULLQ %ZMM3,%ZMM1,%ZMM3 |
0x43a572 VPADDQ %ZMM3,%ZMM7,%ZMM3 |
0x43a578 VXORPD %XMM31,%XMM31,%XMM31 |
0x43a57e KXNORW %K0,%K0,%K2 |
0x43a582 VGATHERQPD (,%ZMM3,1),%ZMM31{%K2} [1] |
0x43a58d VPBROADCASTD %R8D,%YMM30{%K1} |
0x43a593 VANDPD %ZMM4,%ZMM27,%ZMM3 |
0x43a599 VDIVPD %ZMM29,%ZMM3,%ZMM29 |
0x43a59f VPMOVSXDQ %YMM30,%ZMM3 |
0x43a5a5 VPSUBQ %ZMM5,%ZMM3,%ZMM3 |
0x43a5ab VPMULLQ %ZMM3,%ZMM1,%ZMM3 |
0x43a5b1 VPADDQ %ZMM3,%ZMM7,%ZMM3 |
0x43a5b7 VPXORD %XMM30,%XMM30,%XMM30 |
0x43a5bd KXNORW %K0,%K0,%K2 |
0x43a5c1 VGATHERQPD (,%ZMM3,1),%ZMM30{%K2} [6] |
0x43a5cc VXORPD %XMM3,%XMM3,%XMM3 |
0x43a5d0 VSUBPD %ZMM31,%ZMM28,%ZMM7 |
0x43a5d6 VSUBPD %ZMM28,%ZMM30,%ZMM31 |
0x43a5dc VMULPD %ZMM7,%ZMM31,%ZMM30 |
0x43a5e2 VCMPPD $0x1,%ZMM30,%ZMM3,%K0 |
0x43a5e9 KORTESTB %K0,%K0 |
0x43a5ed JE 43a480 |
0x43a5f3 VCMPPD $0x1,%ZMM30,%ZMM12,%K2 |
0x43a5fa VPBLENDMD %YMM24,%YMM23,%YMM8{%K1} |
0x43a600 VMOVSD (%R10,%RDI,8),%XMM2 [8] |
0x43a606 VANDPD %ZMM4,%ZMM7,%ZMM7 |
0x43a60c VANDPD %ZMM4,%ZMM31,%ZMM3 |
0x43a612 VSUBPD %ZMM29,%ZMM13,%ZMM17 |
0x43a618 VMULPD %ZMM17,%ZMM3,%ZMM17 |
0x43a61e VDIVSD %XMM2,%XMM14,%XMM18 |
0x43a624 VBROADCASTSD %XMM18,%ZMM18 |
0x43a62a VCMPPD $0x2,%ZMM3,%ZMM7,%K1 |
0x43a631 VMOVAPD %ZMM7,%ZMM3{%K1} |
0x43a637 VPMOVSXDQ %YMM8,%ZMM8 |
0x43a63d VPSUBQ %ZMM5,%ZMM8,%ZMM8 |
0x43a643 VXORPD %XMM19,%XMM19,%XMM19 |
0x43a649 VGATHERQPD (%R10,%ZMM8,8),%ZMM19{%K2} [7] |
0x43a650 VFMADD213PD %ZMM7,%ZMM29,%ZMM7 |
0x43a656 VDIVPD %ZMM19,%ZMM7,%ZMM7 |
0x43a65c VFMADD231PD %ZMM18,%ZMM17,%ZMM7 |
0x43a662 VMULSD %XMM2,%XMM15,%XMM2 |
0x43a666 VBROADCASTSD %XMM2,%ZMM2 |
0x43a66c VMULPD %ZMM7,%ZMM2,%ZMM2 |
0x43a672 VCMPPD $0x2,%ZMM3,%ZMM2,%K1 |
0x43a679 VMOVAPD %ZMM2,%ZMM3{%K1} |
0x43a67f VFPCLASSPD $0x56,%ZMM31,%K1 |
0x43a686 VXORPD %ZMM16,%ZMM3,%ZMM3{%K1} |
0x43a68c JMP 43a480 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 241 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
215: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
227: sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor)) |
228: width=celldy(k) |
229: vdiffuw=vel1(j,donor)-vel1(j,upwind) |
230: vdiffdw=vel1(j,downwind)-vel1(j,donor) |
231: limiter=0.0 |
232: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
233: auw=ABS(vdiffuw) |
234: adw=ABS(vdiffdw) |
235: wind=1.0_8 |
236: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
237: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw) |
238: ENDIF |
239: advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter |
240: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
241: ENDDO |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.08 |
| CQA speedup if FP arith vectorized | 1.01 |
| CQA speedup if fully vectorized | 1.07 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 35.75 |
| CQA cycles if no scalar integer | 33.25 |
| CQA cycles if FP arith vectorized | 35.56 |
| CQA cycles if fully vectorized | 33.44 |
| Front-end cycles | 18.50 |
| DIV/SQRT cycles | 35.75 |
| P0 cycles | 6.00 |
| P1 cycles | 12.50 |
| P2 cycles | 12.50 |
| P3 cycles | 0.50 |
| P4 cycles | 35.75 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 1.00 |
| P10 cycles | 12.50 |
| P11 cycles | 26.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 37.41 - 63.73 |
| Stall cycles (UFS) | 21.11 - 47.30 |
| Nb insns | 74.00 |
| Nb uops | 111.00 |
| Nb loads | 6.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.71 |
| Nb FLOP add-sub | 28.00 |
| Nb FLOP mul | 24.50 |
| Nb FLOP fma | 16.00 |
| Nb FLOP div | 12.50 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 11.89 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 356.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.50 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.50 |
| Vectorization ratio all | 88.52 |
| Vectorization ratio load | 92.86 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 94.44 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 83.33 |
| Vectorization ratio other | 82.41 |
| Vector-efficiency ratio all | 73.75 |
| Vector-efficiency ratio load | 93.75 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 95.14 |
| Vector-efficiency ratio add_sub | 94.98 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 85.42 |
| Vector-efficiency ratio other | 56.85 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.06 |
| CQA speedup if FP arith vectorized | 1.01 |
| CQA speedup if fully vectorized | 1.08 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P0, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 41.50 |
| CQA cycles if no scalar integer | 39.00 |
| CQA cycles if FP arith vectorized | 41.13 |
| CQA cycles if fully vectorized | 38.56 |
| Front-end cycles | 21.17 |
| DIV/SQRT cycles | 41.50 |
| P0 cycles | 7.00 |
| P1 cycles | 14.00 |
| P2 cycles | 14.00 |
| P3 cycles | 0.50 |
| P4 cycles | 41.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 1.00 |
| P10 cycles | 14.00 |
| P11 cycles | 36.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 43.75 - 88.24 |
| Stall cycles (UFS) | 24.90 - 69.31 |
| Nb insns | 87.00 |
| Nb uops | 127.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.13 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 33.00 |
| Nb FLOP fma | 24.00 |
| Nb FLOP div | 17.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.99 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 392.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 86.84 |
| Vectorization ratio load | 85.71 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 88.89 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 66.67 |
| Vectorization ratio other | 83.33 |
| Vector-efficiency ratio all | 74.10 |
| Vector-efficiency ratio load | 87.50 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 90.28 |
| Vector-efficiency ratio add_sub | 95.31 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 70.83 |
| Vector-efficiency ratio other | 61.16 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.09 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.06 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P0, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:215-215,advec_mom_kernel.f90:227-241 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 30.00 |
| CQA cycles if no scalar integer | 27.50 |
| CQA cycles if FP arith vectorized | 30.00 |
| CQA cycles if fully vectorized | 28.31 |
| Front-end cycles | 15.83 |
| DIV/SQRT cycles | 30.00 |
| P0 cycles | 5.00 |
| P1 cycles | 11.00 |
| P2 cycles | 11.00 |
| P3 cycles | 0.50 |
| P4 cycles | 30.00 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 1.00 |
| P10 cycles | 11.00 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 31.07 - 39.21 |
| Stall cycles (UFS) | 17.32 - 25.29 |
| Nb insns | 61.00 |
| Nb uops | 95.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.13 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.80 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 90.20 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 81.48 |
| Vector-efficiency ratio all | 73.41 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 94.64 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 52.55 |
| Path / |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-241 |
| Module | exec |
| nb instructions | 74 |
| nb uops | 111 |
| loop length | 450 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 9.50 |
| used ymm registers | 5.50 |
| used zmm registers | 20 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.15 |
| micro-operation queue | 18.50 cycles |
| front end | 18.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 35.75 | 6.00 | 12.50 | 12.50 | 0.50 | 35.75 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 12.50 |
| cycles | 35.75 | 6.00 | 12.50 | 12.50 | 0.50 | 35.75 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 12.50 |
| Cycles executing div or sqrt instructions | 26.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 37.41-63.72 |
| Stall cycles | 21.11-47.30 |
| RS full (events) | 35.84-0.84 |
| PRF_FLOAT full (events) | 0.10-49.45 |
| Front-end | 18.50 |
| Dispatch | 35.75 |
| DIV/SQRT | 26.00 |
| Data deps. | 0.00 |
| Overall L1 | 35.75 |
| all | 84% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 70% |
| all | 94% |
| load | 92% |
| store | 100% |
| mul | 90% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 83% |
| other | 95% |
| all | 88% |
| load | 92% |
| store | 100% |
| mul | 94% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 83% |
| other | 82% |
| all | 61% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 93% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 30% |
| all | 88% |
| load | 93% |
| store | 100% |
| mul | 91% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 85% |
| other | 84% |
| all | 73% |
| load | 93% |
| store | 100% |
| mul | 95% |
| add-sub | 94% |
| fma | 100% |
| div/sqrt | 85% |
| other | 56% |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-241 |
| Module | exec |
| nb instructions | 87 |
| nb uops | 127 |
| loop length | 529 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 12 |
| used ymm registers | 6 |
| used zmm registers | 23 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.80 |
| micro-operation queue | 21.17 cycles |
| front end | 21.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 41.50 | 7.00 | 14.00 | 14.00 | 0.50 | 41.50 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 14.00 |
| cycles | 41.50 | 7.00 | 14.00 | 14.00 | 0.50 | 41.50 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 14.00 |
| Cycles executing div or sqrt instructions | 36.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 43.75-88.24 |
| Stall cycles | 24.90-69.31 |
| RS full (events) | 42.07-0.42 |
| PRF_FLOAT full (events) | 0.20-72.25 |
| Front-end | 21.17 |
| Dispatch | 41.50 |
| DIV/SQRT | 36.00 |
| Data deps. | 0.00 |
| Overall L1 | 41.50 |
| all | 85% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 72% |
| all | 88% |
| load | 85% |
| store | 100% |
| mul | 80% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 66% |
| other | 91% |
| all | 86% |
| load | 85% |
| store | 100% |
| mul | 88% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 66% |
| other | 83% |
| all | 61% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 93% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 31% |
| all | 84% |
| load | 87% |
| store | 100% |
| mul | 82% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 70% |
| other | 83% |
| all | 74% |
| load | 87% |
| store | 100% |
| mul | 90% |
| add-sub | 95% |
| fma | 100% |
| div/sqrt | 70% |
| other | 61% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM30,%ZMM12,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM3,%ZMM2{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM29,%ZMM11,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM28,%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM27,%ZMM3,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM2,(%R14,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JA 43a6c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3d80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%R15,%R11,8),%ZMM27 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM27,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA64 %YMM25,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPBROADCASTD %ECX,%YMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPMOVSXDQ %YMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VPMULLQ %ZMM3,%ZMM0,%ZMM7 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| LEA (%RDX,%R11,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVQ %RSI,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPSUBQ %XMM26,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VPSLLQ $0x3,%XMM28,%XMM28 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPBROADCASTQ %XMM28,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDQ %ZMM9,%ZMM28,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM28,%ZMM6,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM7,%ZMM29,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM29,%XMM29,%XMM29 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM7,1),%ZMM29{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM28,%ZMM10,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VMOVDQA64 %YMM23,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPBROADCASTD %R9D,%YMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA64 %YMM24,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPBROADCASTD %R8D,%YMM30{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VANDPD %ZMM4,%ZMM27,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VDIVPD %ZMM29,%ZMM3,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM30,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM30,%XMM30,%XMM30 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM31,%ZMM28,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM28,%ZMM30,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM7,%ZMM31,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM30,%ZMM3,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 43a480 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3b40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VCMPPD $0x1,%ZMM30,%ZMM12,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPBLENDMD %YMM24,%YMM23,%YMM8{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD (%R10,%RDI,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VANDPD %ZMM4,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VANDPD %ZMM4,%ZMM31,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM29,%ZMM13,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM17,%ZMM3,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVSD %XMM2,%XMM14,%XMM18 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VBROADCASTSD %XMM18,%ZMM18 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VCMPPD $0x2,%ZMM3,%ZMM7,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM7,%ZMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM8,%ZMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VXORPD %XMM19,%XMM19,%XMM19 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R10,%ZMM8,8),%ZMM19{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VFMADD213PD %ZMM7,%ZMM29,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM19,%ZMM7,%ZMM7 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VFMADD231PD %ZMM18,%ZMM17,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM2,%XMM15,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VBROADCASTSD %XMM2,%ZMM2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMULPD %ZMM7,%ZMM2,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x2,%ZMM3,%ZMM2,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM2,%ZMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VFPCLASSPD $0x56,%ZMM31,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VXORPD %ZMM16,%ZMM3,%ZMM3{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| JMP 43a480 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3b40> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-241 |
| Module | exec |
| nb instructions | 61 |
| nb uops | 95 |
| loop length | 371 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 5 |
| used zmm registers | 17 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.50 |
| micro-operation queue | 15.83 cycles |
| front end | 15.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 30.00 | 5.00 | 11.00 | 11.00 | 0.50 | 30.00 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 11.00 |
| cycles | 30.00 | 5.00 | 11.00 | 11.00 | 0.50 | 30.00 | 2.00 | 0.50 | 0.50 | 0.50 | 1.00 | 11.00 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 31.07-39.21 |
| Stall cycles | 17.32-25.29 |
| RS full (events) | 29.62-1.27 |
| Front-end | 15.83 |
| Dispatch | 30.00 |
| DIV/SQRT | 16.00 |
| Data deps. | 0.00 |
| Overall L1 | 30.00 |
| all | 83% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 68% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 90% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 81% |
| all | 61% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 93% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 29% |
| all | 92% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 86% |
| all | 73% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 94% |
| fma | 100% |
| div/sqrt | 100% |
| other | 52% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM30,%ZMM12,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM3,%ZMM2{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM29,%ZMM11,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM28,%ZMM2,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM27,%ZMM3,%ZMM2 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM2,(%R14,%R11,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R11 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R12,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JA 43a6c0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3d80> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%R15,%R11,8),%ZMM27 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM27,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA64 %YMM25,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPBROADCASTD %ECX,%YMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPMOVSXDQ %YMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPXOR %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VPMULLQ %ZMM3,%ZMM0,%ZMM7 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| LEA (%RDX,%R11,1),%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVQ %RSI,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPSUBQ %XMM26,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VPSLLQ $0x3,%XMM28,%XMM28 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPBROADCASTQ %XMM28,%ZMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDQ %ZMM9,%ZMM28,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM28,%ZMM6,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM7,%ZMM29,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM29,%XMM29,%XMM29 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM7,1),%ZMM29{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM28,%ZMM10,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VMOVDQA64 %YMM23,%YMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPBROADCASTD %R9D,%YMM3{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA64 %YMM24,%YMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM3,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPBROADCASTD %R8D,%YMM30{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VANDPD %ZMM4,%ZMM27,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VDIVPD %ZMM29,%ZMM3,%ZMM29 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM30,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM3,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPMULLQ %ZMM3,%ZMM1,%ZMM3 | 5 | 1.50 | 0 | 0 | 0 | 0 | 1.50 | 0 | 0 | 0 | 0 | 0 | 0 | 15 | 1.50 |
| VPADDQ %ZMM3,%ZMM7,%ZMM3 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPXORD %XMM30,%XMM30,%XMM30 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VGATHERQPD (,%ZMM3,1),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM31,%ZMM28,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM28,%ZMM30,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM7,%ZMM31,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM30,%ZMM3,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 43a480 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3b40> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
