| Loop Id: 269 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 3.81% |
|---|
| Loop Id: 269 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 3.81% |
|---|
0x439d80 VCMPPD $0x1,%ZMM24,%ZMM8,%K1 |
0x439d87 VMOVAPD %ZMM25,%ZMM23{%K1}{z} |
0x439d8d VSUBPD %ZMM22,%ZMM6,%ZMM22 |
0x439d93 VFMADD213PD %ZMM21,%ZMM23,%ZMM22 |
0x439d99 VMULPD %ZMM20,%ZMM22,%ZMM20 |
0x439d9f VMOVUPD %ZMM20,(%R13,%R14,8) [6] |
0x439da7 ADD $0x8,%R14 |
0x439dab CMP %R9,%R14 |
0x439dae JA 439f40 |
0x439db4 VMOVUPD (%RBX,%R14,8),%ZMM20 [8] |
0x439dbb VFPCLASSPD $0x50,%ZMM20,%K1 |
0x439dc2 LEA (%RDX,%R14,1),%R10D |
0x439dc6 VPBROADCASTD %R10D,%YMM22 |
0x439dcc VPADDD %YMM1,%YMM22,%YMM23 |
0x439dd2 VPADDD %YMM3,%YMM22,%YMM21 |
0x439dd8 VPBLENDMD %YMM21,%YMM23,%YMM24{%K1} |
0x439dde VMOVDQA32 %YMM23,%YMM21{%K1} |
0x439de4 VPMOVSXDQ %YMM21,%ZMM21 |
0x439dea VPSUBQ %ZMM5,%ZMM21,%ZMM25 |
0x439df0 KXNORW %K0,%K0,%K2 |
0x439df4 VXORPD %XMM26,%XMM26,%XMM26 |
0x439dfa VGATHERQPD (%RAX,%ZMM25,8),%ZMM26{%K2} [5] |
0x439e01 KXNORW %K0,%K0,%K2 |
0x439e05 VPXORD %XMM21,%XMM21,%XMM21 |
0x439e0b VGATHERQPD (%RCX,%ZMM25,8),%ZMM21{%K2} [1] |
0x439e12 VPADDD %YMM11,%YMM22,%YMM27 |
0x439e18 VMOVDQA64 %YMM27,%YMM25 |
0x439e1e VPADDD %YMM12,%YMM22,%YMM25{%K1} |
0x439e24 VANDPD %ZMM4,%ZMM20,%ZMM22 |
0x439e2a VPMOVSXDQ %YMM25,%ZMM25 |
0x439e30 VPSUBQ %ZMM5,%ZMM25,%ZMM25 |
0x439e36 KXNORW %K0,%K0,%K2 |
0x439e3a VXORPD %XMM28,%XMM28,%XMM28 |
0x439e40 VGATHERQPD (%RCX,%ZMM25,8),%ZMM28{%K2} [4] |
0x439e47 VDIVPD %ZMM26,%ZMM22,%ZMM22 |
0x439e4d VPMOVSXDQ %YMM24,%ZMM24 |
0x439e53 VPSUBQ %ZMM5,%ZMM24,%ZMM24 |
0x439e59 KXNORW %K0,%K0,%K2 |
0x439e5d VXORPD %XMM26,%XMM26,%XMM26 |
0x439e63 VGATHERQPD (%RCX,%ZMM24,8),%ZMM26{%K2} [2] |
0x439e6a VXORPD %XMM25,%XMM25,%XMM25 |
0x439e70 VSUBPD %ZMM28,%ZMM21,%ZMM28 |
0x439e76 VSUBPD %ZMM21,%ZMM26,%ZMM26 |
0x439e7c VMULPD %ZMM28,%ZMM26,%ZMM24 |
0x439e82 VCMPPD $0x1,%ZMM24,%ZMM25,%K0 |
0x439e89 KORTESTB %K0,%K0 |
0x439e8d JE 439d80 |
0x439e93 VCMPPD $0x1,%ZMM24,%ZMM8,%K2 |
0x439e9a VMOVDQA32 %YMM23,%YMM27{%K1} |
0x439ea0 VMOVUPD (%R8,%R14,8),%ZMM23{%K2}{z} [3] |
0x439ea7 VANDPD %ZMM4,%ZMM28,%ZMM28 |
0x439ead VANDPD %ZMM4,%ZMM26,%ZMM25 |
0x439eb3 VPMOVSXDQ %YMM27,%ZMM27 |
0x439eb9 VPSUBQ %ZMM5,%ZMM27,%ZMM27 |
0x439ebf VXORPD %XMM29,%XMM29,%XMM29 |
0x439ec5 VGATHERQPD (%RDI,%ZMM27,8),%ZMM29{%K2} [7] |
0x439ecc VSUBPD %ZMM22,%ZMM7,%ZMM27 |
0x439ed2 VMULPD %ZMM27,%ZMM25,%ZMM27 |
0x439ed8 VDIVPD %ZMM23,%ZMM27,%ZMM27 |
0x439ede VCMPPD $0x2,%ZMM25,%ZMM28,%K1 |
0x439ee5 VMOVAPD %ZMM28,%ZMM25{%K1} |
0x439eeb VFMADD213PD %ZMM28,%ZMM22,%ZMM28 |
0x439ef1 VDIVPD %ZMM29,%ZMM28,%ZMM28 |
0x439ef7 VADDPD %ZMM27,%ZMM28,%ZMM27 |
0x439efd VMULPD %ZMM9,%ZMM23,%ZMM23 |
0x439f03 VMULPD %ZMM27,%ZMM23,%ZMM23 |
0x439f09 VCMPPD $0x2,%ZMM25,%ZMM23,%K1 |
0x439f10 VMOVAPD %ZMM23,%ZMM25{%K1} |
0x439f16 VFPCLASSPD $0x56,%ZMM26,%K1 |
0x439f1d VXORPD %ZMM10,%ZMM25,%ZMM25{%K1} |
0x439f23 JMP 439d80 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 177 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
152: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
158: upwind=j-1 |
159: donor=j |
160: downwind=j+1 |
161: dif=upwind |
162: ENDIF |
163: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
164: width=celldx(j) |
165: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
166: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
167: limiter=0.0 |
168: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
169: auw=ABS(vdiffuw) |
170: adw=ABS(vdiffdw) |
171: wind=1.0_8 |
172: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
173: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
174: ENDIF |
175: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
176: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
177: ENDDO |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.04 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.01 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 33.25 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 33.25 |
| CQA cycles if fully vectorized | 33.03 |
| Front-end cycles | 13.50 |
| DIV/SQRT cycles | 24.50 |
| P0 cycles | 6.00 |
| P1 cycles | 12.50 |
| P2 cycles | 12.50 |
| P3 cycles | 0.50 |
| P4 cycles | 24.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 12.50 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 34.22 - 180.79 |
| Stall cycles (UFS) | 21.51 - 168.01 |
| Nb insns | 59.00 |
| Nb uops | 81.00 |
| Nb loads | 6.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.01 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 28.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.71 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 384.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.50 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.50 |
| Vectorization ratio all | 97.82 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 96.15 |
| Vector-efficiency ratio all | 77.38 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 82.31 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 67.82 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.57 |
| Bottlenecks | P0, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 48.00 |
| CQA cycles if no scalar integer | 48.00 |
| CQA cycles if FP arith vectorized | 48.00 |
| CQA cycles if fully vectorized | 48.00 |
| Front-end cycles | 16.17 |
| DIV/SQRT cycles | 30.50 |
| P0 cycles | 6.00 |
| P1 cycles | 14.00 |
| P2 cycles | 14.00 |
| P3 cycles | 0.50 |
| P4 cycles | 30.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 14.00 |
| P11 cycles | 48.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 49.19 - 182.27 |
| Stall cycles (UFS) | 33.85 - 167.06 |
| Nb insns | 71.00 |
| Nb uops | 97.00 |
| Nb loads | 7.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.83 |
| Nb FLOP add-sub | 40.00 |
| Nb FLOP mul | 40.00 |
| Nb FLOP fma | 16.00 |
| Nb FLOP div | 24.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 448.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 4.00 |
| Vectorization ratio all | 98.33 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 97.06 |
| Vector-efficiency ratio all | 80.94 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 84.62 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 72.24 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.16 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.02 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P0, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 18.50 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 18.50 |
| CQA cycles if fully vectorized | 18.06 |
| Front-end cycles | 10.83 |
| DIV/SQRT cycles | 18.50 |
| P0 cycles | 6.00 |
| P1 cycles | 11.00 |
| P2 cycles | 11.00 |
| P3 cycles | 0.50 |
| P4 cycles | 18.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 11.00 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 19.25 - 179.32 |
| Stall cycles (UFS) | 9.17 - 168.97 |
| Nb insns | 47.00 |
| Nb uops | 65.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.46 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.76 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 97.30 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 95.24 |
| Vector-efficiency ratio all | 73.82 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 80.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 63.39 |
| Path / |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 59 |
| nb uops | 81 |
| loop length | 349.50 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 4.50 |
| used ymm registers | 10 |
| used zmm registers | 14.50 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.25 |
| micro-operation queue | 13.50 cycles |
| front end | 13.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 24.50 | 6.00 | 12.50 | 12.50 | 0.50 | 24.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 12.50 |
| cycles | 24.50 | 6.00 | 12.50 | 12.50 | 0.50 | 24.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 12.50 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 34.22-180.80 |
| Stall cycles | 21.51-168.01 |
| RS full (events) | 13.54-97.92 |
| PRF_FLOAT full (events) | 15.67-0.00 |
| Front-end | 13.50 |
| Dispatch | 24.50 |
| DIV/SQRT | 32.00 |
| Data deps. | 0.00 |
| Overall L1 | 33.25 |
| all | 93% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 88% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 97% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 96% |
| all | 56% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 73% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 42% |
| all | 88% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 80% |
| all | 77% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 82% |
| fma | 100% |
| div/sqrt | 100% |
| other | 67% |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 71 |
| nb uops | 97 |
| loop length | 424 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 5 |
| used ymm registers | 10 |
| used zmm registers | 17 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 16.17 cycles |
| front end | 16.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 30.50 | 6.00 | 14.00 | 14.00 | 0.50 | 30.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 14.00 |
| cycles | 30.50 | 6.00 | 14.00 | 14.00 | 0.50 | 30.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 14.00 |
| Cycles executing div or sqrt instructions | 48.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 49.19-182.27 |
| Stall cycles | 33.85-167.06 |
| RS full (events) | 9.14-181.66 |
| PRF_FLOAT full (events) | 31.34-0.00 |
| Front-end | 16.17 |
| Dispatch | 30.50 |
| DIV/SQRT | 48.00 |
| Data deps. | 0.00 |
| Overall L1 | 48.00 |
| all | 94% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 90% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 98% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 97% |
| all | 57% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 75% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 43% |
| all | 91% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 84% |
| all | 80% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 84% |
| fma | 100% |
| div/sqrt | 100% |
| other | 72% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM24,%ZMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM25,%ZMM23{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM22,%ZMM6,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM21,%ZMM23,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM20,%ZMM22,%ZMM20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM20,(%R13,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JA 439f40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%RBX,%R14,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM20,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| LEA (%RDX,%R14,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| VPBROADCASTD %R10D,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDD %YMM1,%YMM22,%YMM23 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPADDD %YMM3,%YMM22,%YMM21 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPBLENDMD %YMM21,%YMM23,%YMM24{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA32 %YMM23,%YMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM21,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM21,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RAX,%ZMM25,8),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM21,%XMM21,%XMM21 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%RCX,%ZMM25,8),%ZMM21{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPADDD %YMM11,%YMM22,%YMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA64 %YMM27,%YMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDD %YMM12,%YMM22,%YMM25{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VANDPD %ZMM4,%ZMM20,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPMOVSXDQ %YMM25,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM25,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RCX,%ZMM25,8),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VDIVPD %ZMM26,%ZMM22,%ZMM22 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM24,%ZMM24 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RCX,%ZMM24,8),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM25,%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM28,%ZMM21,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM21,%ZMM26,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM28,%ZMM26,%ZMM24 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM24,%ZMM25,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 439d80 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VCMPPD $0x1,%ZMM24,%ZMM8,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA32 %YMM23,%YMM27{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VMOVUPD (%R8,%R14,8),%ZMM23{%K2}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VANDPD %ZMM4,%ZMM28,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VANDPD %ZMM4,%ZMM26,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPMOVSXDQ %YMM27,%ZMM27 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM27,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VXORPD %XMM29,%XMM29,%XMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RDI,%ZMM27,8),%ZMM29{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VSUBPD %ZMM22,%ZMM7,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM27,%ZMM25,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM23,%ZMM27,%ZMM27 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VCMPPD $0x2,%ZMM25,%ZMM28,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM28,%ZMM25{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VFMADD213PD %ZMM28,%ZMM22,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM29,%ZMM28,%ZMM28 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VADDPD %ZMM27,%ZMM28,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM9,%ZMM23,%ZMM23 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM27,%ZMM23,%ZMM23 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x2,%ZMM25,%ZMM23,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM23,%ZMM25{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VFPCLASSPD $0x56,%ZMM26,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VXORPD %ZMM10,%ZMM25,%ZMM25{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| JMP 439d80 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3440> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 47 |
| nb uops | 65 |
| loop length | 275 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 10 |
| used zmm registers | 12 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.50 |
| micro-operation queue | 10.83 cycles |
| front end | 10.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 18.50 | 6.00 | 11.00 | 11.00 | 0.50 | 18.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 11.00 |
| cycles | 18.50 | 6.00 | 11.00 | 11.00 | 0.50 | 18.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 11.00 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 19.25-179.32 |
| Stall cycles | 9.17-168.97 |
| RS full (events) | 17.93-14.19 |
| Front-end | 10.83 |
| Dispatch | 18.50 |
| DIV/SQRT | 16.00 |
| Data deps. | 0.00 |
| Overall L1 | 18.50 |
| all | 93% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 87% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 97% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 95% |
| all | 55% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 71% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 41% |
| all | 86% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 76% |
| all | 73% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 80% |
| fma | 100% |
| div/sqrt | 100% |
| other | 63% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM24,%ZMM8,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM25,%ZMM23{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM22,%ZMM6,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM21,%ZMM23,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM20,%ZMM22,%ZMM20 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM20,(%R13,%R14,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R14 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R9,%R14 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JA 439f40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3600> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%RBX,%R14,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM20,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| LEA (%RDX,%R14,1),%R10D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| VPBROADCASTD %R10D,%YMM22 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDD %YMM1,%YMM22,%YMM23 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPADDD %YMM3,%YMM22,%YMM21 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPBLENDMD %YMM21,%YMM23,%YMM24{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA32 %YMM23,%YMM21{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM21,%ZMM21 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM21,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RAX,%ZMM25,8),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM21,%XMM21,%XMM21 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%RCX,%ZMM25,8),%ZMM21{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPADDD %YMM11,%YMM22,%YMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA64 %YMM27,%YMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDD %YMM12,%YMM22,%YMM25{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VANDPD %ZMM4,%ZMM20,%ZMM22 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPMOVSXDQ %YMM25,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM25,%ZMM25 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM28,%XMM28,%XMM28 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RCX,%ZMM25,8),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VDIVPD %ZMM26,%ZMM22,%ZMM22 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM24,%ZMM24 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM5,%ZMM24,%ZMM24 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM26,%XMM26,%XMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%RCX,%ZMM24,8),%ZMM26{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM25,%XMM25,%XMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM28,%ZMM21,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM21,%ZMM26,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM28,%ZMM26,%ZMM24 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM24,%ZMM25,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 439d80 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
