| Loop Id: 144 | Module: exec | Source: advec_mom_kernel.f90:143-144 | Coverage: 3.12% |
|---|
| Loop Id: 144 | Module: exec | Source: advec_mom_kernel.f90:143-144 | Coverage: 3.12% |
|---|
0x436a40 VMOVUPD (%RSI,%RDX,1),%ZMM9 [11] |
0x436a47 VMOVUPD (%R12,%RDX,1),%ZMM11 [12] |
0x436a4e VMOVUPD (%RBX,%RDX,1),%ZMM10 [8] |
0x436a55 VMOVUPD (%R10,%RDX,1),%ZMM15 [8] |
0x436a5c VMULPD (%RCX,%RDX,1),%ZMM9,%ZMM13 [5] |
0x436a63 MOV 0x188(%RSP),%R15 [13] |
0x436a6b VMULPD (%R13,%RDX,1),%ZMM11,%ZMM12 [6] |
0x436a73 VFMADD231PD (%R11,%RDX,1),%ZMM10,%ZMM13 [1] |
0x436a7a VFMADD231PD (%R9,%RDX,1),%ZMM15,%ZMM12 [2] |
0x436a81 VADDPD %ZMM12,%ZMM13,%ZMM1 |
0x436a87 VMULPD %ZMM2,%ZMM1,%ZMM5 |
0x436a8d VMOVUPD %ZMM5,(%R8,%RDX,1) [7] |
0x436a94 VMOVUPD (%R14,%RDX,1),%ZMM8 [3] |
0x436a9b VSUBPD (%RAX,%RDX,1),%ZMM8,%ZMM0 [10] |
0x436aa2 VADDPD %ZMM5,%ZMM0,%ZMM6 |
0x436aa8 VMOVUPD %ZMM6,(%RDI,%RDX,1) [9] |
0x436aaf VMOVUPD 0x40(%RSI,%RDX,1),%ZMM7 [11] |
0x436ab7 VMOVUPD 0x40(%R12,%RDX,1),%ZMM13 [12] |
0x436abf VMOVUPD 0x40(%RBX,%RDX,1),%ZMM9 [8] |
0x436ac7 VMOVUPD 0x40(%R10,%RDX,1),%ZMM11 [8] |
0x436acf VMULPD 0x40(%RDX,%RCX,1),%ZMM7,%ZMM14 [4] |
0x436ad7 VMULPD 0x40(%R13,%RDX,1),%ZMM13,%ZMM10 [6] |
0x436adf VFMADD231PD 0x40(%R11,%RDX,1),%ZMM9,%ZMM14 [1] |
0x436ae7 VFMADD231PD 0x40(%R9,%RDX,1),%ZMM11,%ZMM10 [2] |
0x436aef VADDPD %ZMM10,%ZMM14,%ZMM12 |
0x436af5 VMULPD %ZMM2,%ZMM12,%ZMM15 |
0x436afb VMOVUPD %ZMM15,0x40(%R8,%RDX,1) [7] |
0x436b03 VMOVUPD 0x40(%R14,%RDX,1),%ZMM1 [3] |
0x436b0b VSUBPD 0x40(%RAX,%RDX,1),%ZMM1,%ZMM5 [10] |
0x436b13 VADDPD %ZMM15,%ZMM5,%ZMM8 |
0x436b19 VMOVUPD %ZMM8,0x40(%RDI,%RDX,1) [9] |
0x436b21 SUB $-0x80,%RDX |
0x436b25 CMP %R15,%RDX |
0x436b28 JNE 436a40 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 143 - 144 |
-------------------------------------------------------------------------------- |
143: +density1(j-1,k )*post_vol(j-1,k )) |
144: node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j-1,k)+node_flux(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.12 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:143-144 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 7.17 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 7.00 |
| P2 cycles | 7.00 |
| P3 cycles | 2.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 7.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.32 |
| Stall cycles (UFS) | 0.51 |
| Nb insns | 34.00 |
| Nb uops | 33.00 |
| Nb loads | 21.00 |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 20.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 48.00 |
| Nb FLOP fma | 32.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 193.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1288.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 11.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.12 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel._omp_fn.0 |
| Source | advec_mom_kernel.f90:143-144 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 7.17 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 7.00 |
| P2 cycles | 7.00 |
| P3 cycles | 2.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 0.00 |
| P10 cycles | 7.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.32 |
| Stall cycles (UFS) | 0.51 |
| Nb insns | 34.00 |
| Nb uops | 33.00 |
| Nb loads | 21.00 |
| Nb stores | 4.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 20.00 |
| Nb FLOP add-sub | 48.00 |
| Nb FLOP mul | 48.00 |
| Nb FLOP fma | 32.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 193.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1288.00 |
| Bytes stored | 256.00 |
| Stride 0 | 1.00 |
| Stride 1 | 11.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:143-144 |
| Module | exec |
| nb instructions | 34 |
| nb uops | 33 |
| loop length | 238 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 7.17 cycles |
| front end | 7.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.00 | 7.00 | 7.00 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 7.00 |
| cycles | 8.00 | 8.00 | 7.00 | 7.00 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.32 |
| Stall cycles | 0.51 |
| LB full (events) | 0.81 |
| Front-end | 7.17 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RSI,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R12,%RDX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%RDX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%RDX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%RCX,%RDX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x188(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R13,%RDX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R11,%RDX,1),%ZMM10,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R9,%RDX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %ZMM12,%ZMM13,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM2,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM5,(%R8,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%R14,%RDX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%RAX,%RDX,1),%ZMM8,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM5,%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %ZMM6,(%RDI,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%RSI,%RDX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R12,%RDX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RBX,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R10,%RDX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD 0x40(%RDX,%RCX,1),%ZMM7,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD 0x40(%R13,%RDX,1),%ZMM13,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD 0x40(%R11,%RDX,1),%ZMM9,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD 0x40(%R9,%RDX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %ZMM10,%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM2,%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM15,0x40(%R8,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R14,%RDX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD 0x40(%RAX,%RDX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM15,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %ZMM8,0x40(%RDI,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| SUB $-0x80,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 436a40 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x4820> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_mom_kernel._omp_fn.0 |
| Source file and lines | advec_mom_kernel.f90:143-144 |
| Module | exec |
| nb instructions | 34 |
| nb uops | 33 |
| loop length | 238 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 7.17 cycles |
| front end | 7.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 0.00 | 7.00 | 7.00 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 7.00 |
| cycles | 8.00 | 8.00 | 7.00 | 7.00 | 2.00 | 8.00 | 1.00 | 2.00 | 2.00 | 2.00 | 0.00 | 7.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.32 |
| Stall cycles | 0.51 |
| LB full (events) | 0.81 |
| Front-end | 7.17 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%RSI,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R12,%RDX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RBX,%RDX,1),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%RDX,1),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%RCX,%RDX,1),%ZMM9,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x188(%RSP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R13,%RDX,1),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R11,%RDX,1),%ZMM10,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%R9,%RDX,1),%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %ZMM12,%ZMM13,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM2,%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM5,(%R8,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD (%R14,%RDX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD (%RAX,%RDX,1),%ZMM8,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM5,%ZMM0,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %ZMM6,(%RDI,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%RSI,%RDX,1),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R12,%RDX,1),%ZMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%RBX,%RDX,1),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R10,%RDX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD 0x40(%RDX,%RCX,1),%ZMM7,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD 0x40(%R13,%RDX,1),%ZMM13,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD 0x40(%R11,%RDX,1),%ZMM9,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD 0x40(%R9,%RDX,1),%ZMM11,%ZMM10 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD %ZMM10,%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM2,%ZMM12,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM15,0x40(%R8,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD 0x40(%R14,%RDX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD 0x40(%RAX,%RDX,1),%ZMM1,%ZMM5 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM15,%ZMM5,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %ZMM8,0x40(%RDI,%RDX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| SUB $-0x80,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 436a40 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x4820> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
