| Loop Id: 239 | Module: exec | Source: advec_cell_kernel.f90:255-261 | Coverage: 3.59% |
|---|
| Loop Id: 239 | Module: exec | Source: advec_cell_kernel.f90:255-261 | Coverage: 3.59% |
|---|
0x42e7c0 VMOVUPD (%R12,%RDX,8),%ZMM11 [3] |
0x42e7c7 VMULPD (%R11,%RDX,8),%ZMM11,%ZMM12 [7] |
0x42e7ce VADDPD (%R9,%RDX,8),%ZMM12,%ZMM13 [8] |
0x42e7d5 VSUBPD (%RCX,%RDX,8),%ZMM13,%ZMM13 [6] |
0x42e7dc VMOVUPD (%RDI,%RDX,8),%ZMM14 [4] |
0x42e7e3 VFMADD213PD (%RAX,%RDX,8),%ZMM12,%ZMM14 [1] |
0x42e7ea VSUBPD (%R10,%RDX,8),%ZMM14,%ZMM12 [5] |
0x42e7f1 VDIVPD %ZMM13,%ZMM12,%ZMM12 |
0x42e7f7 VADDPD (%R8,%RDX,8),%ZMM11,%ZMM11 [2] |
0x42e7fe VSUBPD (%R13,%RDX,8),%ZMM11,%ZMM11 [9] |
0x42e806 VDIVPD %ZMM11,%ZMM13,%ZMM11 |
0x42e80c VMOVUPD %ZMM11,(%R11,%RDX,8) [7] |
0x42e813 VMOVUPD %ZMM12,(%RDI,%RDX,8) [4] |
0x42e81a ADD $0x8,%RDX |
0x42e81e CMP %RBX,%RDX |
0x42e821 JB 42e7c0 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 255 - 261 |
-------------------------------------------------------------------------------- |
255: DO j=x_min,x_max |
256: pre_mass_s=density1(j,k)*pre_vol(j,k) |
257: post_mass_s=pre_mass_s+mass_flux_y(j,k)-mass_flux_y(j,k+1) |
258: post_ener_s=(energy1(j,k)*pre_mass_s+ener_flux(j,k)-ener_flux(j,k+1))/post_mass_s |
259: advec_vol_s=pre_vol(j,k)+vol_flux_y(j,k)-vol_flux_y(j,k+1) |
260: density1(j,k)=post_mass_s/advec_vol_s |
261: energy1(j,k)=post_ener_s |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.92 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:255-261 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 32.00 |
| CQA cycles if fully vectorized | 32.00 |
| Front-end cycles | 4.33 |
| DIV/SQRT cycles | 6.50 |
| P0 cycles | 3.50 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 6.50 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 32.29 - 32.31 |
| Stall cycles (UFS) | 27.11 - 27.13 |
| Nb insns | 16.00 |
| Nb uops | 19.00 |
| Nb loads | 9.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.50 |
| Nb FLOP add-sub | 40.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 576.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 9.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 4.92 |
| Bottlenecks | P0, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:255-261 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 32.00 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 32.00 |
| CQA cycles if fully vectorized | 32.00 |
| Front-end cycles | 4.33 |
| DIV/SQRT cycles | 6.50 |
| P0 cycles | 3.50 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 1.00 |
| P4 cycles | 6.50 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 32.29 - 32.31 |
| Stall cycles (UFS) | 27.11 - 27.13 |
| Nb insns | 16.00 |
| Nb uops | 19.00 |
| Nb loads | 9.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 2.50 |
| Nb FLOP add-sub | 40.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 576.00 |
| Bytes stored | 128.00 |
| Stride 0 | 0.00 |
| Stride 1 | 9.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:255-261 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 19 |
| loop length | 99 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 4.33 cycles |
| front end | 4.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 6.50 | 0.00 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| cycles | 6.50 | 3.50 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 32.29-32.31 |
| Stall cycles | 27.11-27.13 |
| ROB full (events) | 28.34-28.36 |
| RS full (events) | 0.15 |
| Front-end | 4.33 |
| Dispatch | 6.50 |
| DIV/SQRT | 32.00 |
| Data deps. | 1.00 |
| Overall L1 | 32.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%RDX,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%R11,%RDX,8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD (%R9,%RDX,8),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RCX,%RDX,8),%ZMM13,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDI,%RDX,8),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD213PD (%RAX,%RDX,8),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBPD (%R10,%RDX,8),%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VDIVPD %ZMM13,%ZMM12,%ZMM12 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VADDPD (%R8,%RDX,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%R13,%RDX,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VDIVPD %ZMM11,%ZMM13,%ZMM11 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD %ZMM11,(%R11,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD %ZMM12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RBX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 42e7c0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x1400> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:255-261 |
| Module | exec |
| nb instructions | 16 |
| nb uops | 19 |
| loop length | 99 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 4 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 5.00 |
| micro-operation queue | 4.33 cycles |
| front end | 4.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 6.50 | 0.00 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| cycles | 6.50 | 3.50 | 3.00 | 3.00 | 1.00 | 6.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 32.29-32.31 |
| Stall cycles | 27.11-27.13 |
| ROB full (events) | 28.34-28.36 |
| RS full (events) | 0.15 |
| Front-end | 4.33 |
| Dispatch | 6.50 |
| DIV/SQRT | 32.00 |
| Data deps. | 1.00 |
| Overall L1 | 32.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%RDX,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%R11,%RDX,8),%ZMM11,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDPD (%R9,%RDX,8),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%RCX,%RDX,8),%ZMM13,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDI,%RDX,8),%ZMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD213PD (%RAX,%RDX,8),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VSUBPD (%R10,%RDX,8),%ZMM14,%ZMM12 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VDIVPD %ZMM13,%ZMM12,%ZMM12 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VADDPD (%R8,%RDX,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD (%R13,%RDX,8),%ZMM11,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VDIVPD %ZMM11,%ZMM13,%ZMM11 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD %ZMM11,(%R11,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| VMOVUPD %ZMM12,(%RDI,%RDX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RBX,%RDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 42e7c0 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x1400> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
