| Loop Id: 273 | Module: exec | Source: advec_mom_kernel.f90:128-131 | Coverage: 0.95% |
|---|
| Loop Id: 273 | Module: exec | Source: advec_mom_kernel.f90:128-131 | Coverage: 0.95% |
|---|
0x4395b0 VMOVUPD -0x8(%R10,%RAX,8),%ZMM6 [2] |
0x4395bb VADDPD -0x8(%RDI,%RAX,8),%ZMM6,%ZMM6 [3] |
0x4395c6 VADDPD (%RDI,%RAX,8),%ZMM6,%ZMM6 [3] |
0x4395cd VADDPD (%R10,%RAX,8),%ZMM6,%ZMM6 [2] |
0x4395d4 VMULPD %ZMM1,%ZMM6,%ZMM6 |
0x4395da VMOVUPD %ZMM6,(%R8,%RAX,8) [1] |
0x4395e1 ADD $0x8,%RAX |
0x4395e5 CMP %R15,%RAX |
0x4395e8 JB 4395b0 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 128 - 131 |
-------------------------------------------------------------------------------- |
128: DO j=x_min-2,x_max+2 |
129: ! Find staggered mesh mass fluxes, nodal masses and volumes. |
130: node_flux(j,k)=0.25_8*(mass_flux_x(j,k-1 )+mass_flux_x(j ,k) & |
131: +mass_flux_x(j+1,k-1)+mass_flux_x(j+1,k)) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:128-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 1.83 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 1.33 |
| P2 cycles | 1.33 |
| P3 cycles | 0.50 |
| P4 cycles | 2.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.00 |
| P10 cycles | 1.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 2.33 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 9.00 |
| Nb uops | 8.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 16.00 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 160.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | P0, P1, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:128-131 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 2.00 |
| Front-end cycles | 1.83 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 1.33 |
| P2 cycles | 1.33 |
| P3 cycles | 0.50 |
| P4 cycles | 2.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 0.00 |
| P10 cycles | 1.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 2.33 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 9.00 |
| Nb uops | 8.00 |
| Nb loads | 4.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 16.00 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 8.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 160.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 256.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 2.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:128-131 |
| Module | exec |
| nb instructions | 9 |
| nb uops | 8 |
| loop length | 58 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 2 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 1.83 cycles |
| front end | 1.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 0.00 | 1.33 | 1.33 | 0.50 | 2.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 1.33 |
| cycles | 2.00 | 2.00 | 1.33 | 1.33 | 0.50 | 2.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 1.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 2.33 |
| Stall cycles | 0.00 |
| Front-end | 1.83 |
| Dispatch | 2.00 |
| Data deps. | 1.00 |
| Overall L1 | 2.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%R10,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD -0x8(%RDI,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RDI,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%R10,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD %ZMM1,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM6,(%R8,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 4395b0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2c70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:128-131 |
| Module | exec |
| nb instructions | 9 |
| nb uops | 8 |
| loop length | 58 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 2 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 3.00 |
| micro-operation queue | 1.83 cycles |
| front end | 1.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 0.00 | 1.33 | 1.33 | 0.50 | 2.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 1.33 |
| cycles | 2.00 | 2.00 | 1.33 | 1.33 | 0.50 | 2.00 | 1.00 | 0.50 | 0.50 | 0.50 | 0.00 | 1.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 2.33 |
| Stall cycles | 0.00 |
| Front-end | 1.83 |
| Dispatch | 2.00 |
| Data deps. | 1.00 |
| Overall L1 | 2.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD -0x8(%R10,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD -0x8(%RDI,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RDI,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%R10,%RAX,8),%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMULPD %ZMM1,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM6,(%R8,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 4395b0 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x2c70> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
