| Loop Id: 193 | Module: exec | Source: field_summary_kernel.f90:62-71 | Coverage: 0.29% |
|---|
| Loop Id: 193 | Module: exec | Source: field_summary_kernel.f90:62-71 | Coverage: 0.29% |
|---|
0x43d5d0 VMOVUPD (%R11,%RAX,8),%XMM13 [2] |
0x43d5d6 VMOVUPD (%R9,%RAX,8),%XMM3 [1] |
0x43d5dc LEA 0x1(%RAX),%RDX |
0x43d5e0 VMOVUPD (%RBX,%RAX,8),%XMM12 [9] |
0x43d5e5 VMOVUPD (%R10,%RAX,8),%XMM10 [10] |
0x43d5eb VMULPD %XMM13,%XMM13,%XMM14 |
0x43d5f0 VMULPD %XMM3,%XMM3,%XMM11 |
0x43d5f4 VMOVUPD (%RBX,%RDX,8),%XMM3 [11] |
0x43d5f9 VFMADD132PD %XMM12,%XMM14,%XMM12 |
0x43d5fe VFMADD132PD %XMM10,%XMM11,%XMM10 |
0x43d603 VMOVUPD (%R11,%RDX,8),%XMM11 [6] |
0x43d609 VMULPD %XMM4,%XMM12,%XMM15 |
0x43d60d VMULPD %XMM4,%XMM10,%XMM12 |
0x43d611 VUNPCKHPD %XMM15,%XMM15,%XMM1 |
0x43d616 VUNPCKHPD %XMM12,%XMM12,%XMM13 |
0x43d61b VADDPD %XMM15,%XMM1,%XMM0 |
0x43d620 VMOVSD (%R8,%RAX,8),%XMM1 [12] |
0x43d626 VADDPD %XMM12,%XMM13,%XMM14 |
0x43d62b VMULPD %XMM11,%XMM11,%XMM12 |
0x43d630 VMULSD (%RDI,%RAX,8),%XMM1,%XMM10 [7] |
0x43d635 VFMADD231SD (%RCX,%RAX,8),%XMM1,%XMM2 [5] |
0x43d63b VADDSD %XMM1,%XMM8,%XMM8 |
0x43d63f VMOVUPD (%R10,%RDX,8),%XMM1 [15] |
0x43d645 VADDSD %XMM14,%XMM0,%XMM15 |
0x43d64a VFMADD132PD %XMM3,%XMM12,%XMM3 |
0x43d64f VMULSD %XMM5,%XMM15,%XMM0 |
0x43d653 VFMADD231SD (%RSI,%RAX,8),%XMM10,%XMM6 [8] |
0x43d659 VADDSD %XMM10,%XMM7,%XMM7 |
0x43d65e ADD $0x2,%RAX |
0x43d662 VMULPD %XMM4,%XMM3,%XMM13 |
0x43d666 VFMADD231SD %XMM0,%XMM10,%XMM9 |
0x43d66b VMOVUPD (%R9,%RDX,8),%XMM10 [13] |
0x43d671 VMULPD %XMM10,%XMM10,%XMM0 |
0x43d676 VUNPCKHPD %XMM13,%XMM13,%XMM14 |
0x43d67b VADDPD %XMM13,%XMM14,%XMM15 |
0x43d680 VMOVSD (%R8,%RDX,8),%XMM14 [16] |
0x43d686 VFMADD132PD %XMM1,%XMM0,%XMM1 |
0x43d68b VFMADD231SD (%RCX,%RDX,8),%XMM14,%XMM2 [4] |
0x43d691 VADDSD %XMM14,%XMM8,%XMM8 |
0x43d696 VMULPD %XMM4,%XMM1,%XMM11 |
0x43d69a VUNPCKHPD %XMM11,%XMM11,%XMM3 |
0x43d69f VADDPD %XMM11,%XMM3,%XMM12 |
0x43d6a4 VADDSD %XMM12,%XMM15,%XMM13 |
0x43d6a9 VMULSD (%RDI,%RDX,8),%XMM14,%XMM15 [14] |
0x43d6ae VMULSD %XMM5,%XMM13,%XMM1 |
0x43d6b2 VFMADD231SD (%RSI,%RDX,8),%XMM15,%XMM6 [3] |
0x43d6b8 VADDSD %XMM15,%XMM7,%XMM7 |
0x43d6bd VFMADD231SD %XMM1,%XMM15,%XMM9 |
0x43d6c2 CMP %EAX,%R12D |
0x43d6c5 JGE 43d5d0 |
/home/eoseret/qaas_runs_CPU_9468/171-152-3172/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71 |
-------------------------------------------------------------------------------- |
62: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
63: ENDDO |
64: ENDDO |
65: cell_vol=volume(j,k) |
66: cell_mass=cell_vol*density0(j,k) |
67: vol=vol+cell_vol |
68: mass=mass+cell_mass |
69: ie=ie+cell_mass*energy0(j,k) |
70: ke=ke+cell_mass*0.5*vsqrd |
71: press=press+cell_vol*pressure(j,k) |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 3.00 |
| CQA speedup if fully vectorized | 5.33 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.28 |
| Bottlenecks | P1, |
| Function | field_summary_kernel._omp_fn.0 |
| Source | field_summary_kernel.f90:62-71 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 9.17 |
| DIV/SQRT cycles | 12.50 |
| P0 cycles | 16.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 0.00 |
| P4 cycles | 11.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 12.56 |
| Stall cycles (UFS) | 2.76 |
| Nb insns | 50.00 |
| Nb uops | 49.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.88 |
| Nb FLOP add-sub | 14.00 |
| Nb FLOP mul | 20.00 |
| Nb FLOP fma | 14.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 8.00 |
| Stride n | 8.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 52.17 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 40.00 |
| Vectorization ratio fma | 40.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 19.02 |
| Vector-efficiency ratio load | 18.75 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 20.83 |
| Vector-efficiency ratio add_sub | 17.50 |
| Vector-efficiency ratio fma | 17.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 3.00 |
| CQA speedup if fully vectorized | 5.33 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.28 |
| Bottlenecks | P1, |
| Function | field_summary_kernel._omp_fn.0 |
| Source | field_summary_kernel.f90:62-71 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 16.00 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 9.17 |
| DIV/SQRT cycles | 12.50 |
| P0 cycles | 16.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 0.00 |
| P4 cycles | 11.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 8 |
| FE+BE cycles (UFS) | 12.56 |
| Stall cycles (UFS) | 2.76 |
| Nb insns | 50.00 |
| Nb uops | 49.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.88 |
| Nb FLOP add-sub | 14.00 |
| Nb FLOP mul | 20.00 |
| Nb FLOP fma | 14.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 12.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 8.00 |
| Stride n | 8.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 52.17 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 66.67 |
| Vectorization ratio add_sub | 40.00 |
| Vectorization ratio fma | 40.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 19.02 |
| Vector-efficiency ratio load | 18.75 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 20.83 |
| Vector-efficiency ratio add_sub | 17.50 |
| Vector-efficiency ratio fma | 17.50 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | field_summary_kernel._omp_fn.0 |
| Source file and lines | field_summary_kernel.f90:62-71 |
| Module | exec |
| nb instructions | 50 |
| nb uops | 49 |
| loop length | 251 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.83 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 12.50 | 12.50 | 5.33 | 5.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| cycles | 12.50 | 16.00 | 5.33 | 5.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 12.56 |
| Stall cycles | 2.76 |
| RS full (events) | 10.05 |
| PRF_FLOAT full (events) | 0.01 |
| Front-end | 9.17 |
| Dispatch | 16.00 |
| Data deps. | 8.00 |
| Overall L1 | 16.00 |
| all | 52% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 66% |
| add-sub | 40% |
| fma | 40% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 19% |
| load | 18% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 20% |
| add-sub | 17% |
| fma | 17% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R11,%RAX,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R9,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVUPD (%RBX,%RAX,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R10,%RAX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM13,%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %XMM3,%XMM3,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%RBX,%RDX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMADD132PD %XMM12,%XMM14,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD132PD %XMM10,%XMM11,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R11,%RDX,8),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM4,%XMM12,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %XMM4,%XMM10,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VUNPCKHPD %XMM12,%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM15,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD (%R8,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %XMM12,%XMM13,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %XMM11,%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD (%RDI,%RAX,8),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231SD (%RCX,%RAX,8),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM1,%XMM8,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R10,%RDX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDSD %XMM14,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD132PD %XMM3,%XMM12,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM5,%XMM15,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RSI,%RAX,8),%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM10,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULPD %XMM4,%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD %XMM0,%XMM10,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R9,%RDX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM10,%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM13,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM13,%XMM14,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD (%R8,%RDX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD %XMM1,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RCX,%RDX,8),%XMM14,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM14,%XMM8,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %XMM4,%XMM1,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM11,%XMM11,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM11,%XMM3,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM12,%XMM15,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%RDI,%RDX,8),%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM5,%XMM13,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RSI,%RDX,8),%XMM15,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM15,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD231SD %XMM1,%XMM15,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %EAX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 43d5d0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | field_summary_kernel._omp_fn.0 |
| Source file and lines | field_summary_kernel.f90:62-71 |
| Module | exec |
| nb instructions | 50 |
| nb uops | 49 |
| loop length | 251 |
| used x86 registers | 11 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.83 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 12.50 | 12.50 | 5.33 | 5.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| cycles | 12.50 | 16.00 | 5.33 | 5.33 | 0.00 | 11.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 8.00 |
| FE+BE cycles | 12.56 |
| Stall cycles | 2.76 |
| RS full (events) | 10.05 |
| PRF_FLOAT full (events) | 0.01 |
| Front-end | 9.17 |
| Dispatch | 16.00 |
| Data deps. | 8.00 |
| Overall L1 | 16.00 |
| all | 52% |
| load | 50% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 66% |
| add-sub | 40% |
| fma | 40% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| all | 19% |
| load | 18% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 20% |
| add-sub | 17% |
| fma | 17% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R11,%RAX,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R9,%RAX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| LEA 0x1(%RAX),%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVUPD (%RBX,%RAX,8),%XMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R10,%RAX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM13,%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %XMM3,%XMM3,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%RBX,%RDX,8),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VFMADD132PD %XMM12,%XMM14,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD132PD %XMM10,%XMM11,%XMM10 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R11,%RDX,8),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM4,%XMM12,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %XMM4,%XMM10,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM15,%XMM15,%XMM1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VUNPCKHPD %XMM12,%XMM12,%XMM13 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM15,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD (%R8,%RAX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %XMM12,%XMM13,%XMM14 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %XMM11,%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD (%RDI,%RAX,8),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231SD (%RCX,%RAX,8),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM1,%XMM8,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R10,%RDX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDSD %XMM14,%XMM0,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD132PD %XMM3,%XMM12,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULSD %XMM5,%XMM15,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RSI,%RAX,8),%XMM10,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM10,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x2,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULPD %XMM4,%XMM3,%XMM13 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD %XMM0,%XMM10,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD (%R9,%RDX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMULPD %XMM10,%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM13,%XMM13,%XMM14 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM13,%XMM14,%XMM15 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVSD (%R8,%RDX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD %XMM1,%XMM0,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RCX,%RDX,8),%XMM14,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM14,%XMM8,%XMM8 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %XMM4,%XMM1,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VUNPCKHPD %XMM11,%XMM11,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VADDPD %XMM11,%XMM3,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM12,%XMM15,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD (%RDI,%RDX,8),%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM5,%XMM13,%XMM1 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231SD (%RSI,%RDX,8),%XMM15,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM15,%XMM7,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD231SD %XMM1,%XMM15,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| CMP %EAX,%R12D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 43d5d0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x2f0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
