| Loop Id: 141 | Module: exec | Source: advec_cell_kernel.f90:181-183 | Coverage: 1.5% |
|---|
| Loop Id: 141 | Module: exec | Source: advec_cell_kernel.f90:181-183 | Coverage: 1.5% |
|---|
0x427010 VMOVUPD (%R12,%R9,8),%YMM7 [3] |
0x427016 VMOVUPD (%R10,%R9,8),%YMM8 [4] |
0x42701c VADDPD (%RDX,%R9,8),%YMM7,%YMM9 [2] |
0x427022 VADDPD (%R15,%R9,8),%YMM9,%YMM9 [5] |
0x427028 VADDPD -0x8(%R15,%R9,8),%YMM8,%YMM10 [5] |
0x42702f VSUBPD %YMM10,%YMM9,%YMM9 |
0x427034 VMOVUPD %YMM9,(%RBX,%R9,8) [1] |
0x42703a VSUBPD %YMM7,%YMM8,%YMM7 |
0x42703e VADDPD %YMM7,%YMM9,%YMM7 |
0x427042 VMOVUPD %YMM7,(%R14,%R9,8) [6] |
0x427048 ADD $0x4,%R9 |
0x42704c CMP %R8,%R9 |
0x42704f JB 427010 |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 181 - 183 |
-------------------------------------------------------------------------------- |
181: DO j=x_min-2,x_max+2 |
182: pre_vol(j,k)=volume(j,k)+(vol_flux_y(j ,k+1)-vol_flux_y(j,k)+vol_flux_x(j+1,k )-vol_flux_x(j,k)) |
183: post_vol(j,k)=pre_vol(j,k)-(vol_flux_y(j ,k+1)-vol_flux_y(j,k)) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.69 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.20 |
| Bottlenecks | P1, P5, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:181-183 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.00 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 1.78 |
| CQA cycles if fully vectorized | 1.50 |
| Front-end cycles | 2.50 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 3.00 |
| P1 cycles | 1.67 |
| P2 cycles | 1.67 |
| P3 cycles | 1.00 |
| P4 cycles | 3.00 |
| P5 cycles | 0.50 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 1.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.36 |
| Stall cycles (UFS) | 0.16 |
| Nb insns | 13.00 |
| Nb uops | 12.00 |
| Nb loads | 5.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 74.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.69 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.20 |
| Bottlenecks | P1, P5, |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_cell_kernel.f90:181-183 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.00 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 1.78 |
| CQA cycles if fully vectorized | 1.50 |
| Front-end cycles | 2.50 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 3.00 |
| P1 cycles | 1.67 |
| P2 cycles | 1.67 |
| P3 cycles | 1.00 |
| P4 cycles | 3.00 |
| P5 cycles | 0.50 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 1.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.36 |
| Stall cycles (UFS) | 0.16 |
| Nb insns | 13.00 |
| Nb uops | 12.00 |
| Nb loads | 5.00 |
| Nb stores | 2.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 8.00 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 74.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 160.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 5.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:181-183 |
| Module | exec |
| nb instructions | 13 |
| nb uops | 12 |
| loop length | 65 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 4 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 2.50 cycles |
| front end | 2.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 3.00 | 1.67 | 1.67 | 1.00 | 3.00 | 0.50 | 1.00 | 1.00 | 1.00 | 0.00 | 1.67 |
| cycles | 0.50 | 3.00 | 1.67 | 1.67 | 1.00 | 3.00 | 0.50 | 1.00 | 1.00 | 1.00 | 0.00 | 1.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.36 |
| Stall cycles | 0.16 |
| RS full (events) | 0.62 |
| Front-end | 2.50 |
| Dispatch | 3.00 |
| Data deps. | 1.00 |
| Overall L1 | 3.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%R9,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R10,%R9,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RDX,%R9,8),%YMM7,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R15,%R9,8),%YMM9,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD -0x8(%R15,%R9,8),%YMM8,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD %YMM10,%YMM9,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM9,(%RBX,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VSUBPD %YMM7,%YMM8,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM7,(%R14,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x4,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R8,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 427010 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x13b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | advec_cell_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_cell_kernel.f90:181-183 |
| Module | exec |
| nb instructions | 13 |
| nb uops | 12 |
| loop length | 65 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 4 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 2.50 cycles |
| front end | 2.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 3.00 | 1.67 | 1.67 | 1.00 | 3.00 | 0.50 | 1.00 | 1.00 | 1.00 | 0.00 | 1.67 |
| cycles | 0.50 | 3.00 | 1.67 | 1.67 | 1.00 | 3.00 | 0.50 | 1.00 | 1.00 | 1.00 | 0.00 | 1.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.36 |
| Stall cycles | 0.16 |
| RS full (events) | 0.62 |
| Front-end | 2.50 |
| Dispatch | 3.00 |
| Data deps. | 1.00 |
| Overall L1 | 3.00 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R12,%R9,8),%YMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD (%R10,%R9,8),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RDX,%R9,8),%YMM7,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD (%R15,%R9,8),%YMM9,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDPD -0x8(%R15,%R9,8),%YMM8,%YMM10 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VSUBPD %YMM10,%YMM9,%YMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM9,(%RBX,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VSUBPD %YMM7,%YMM8,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %YMM7,%YMM9,%YMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD %YMM7,(%R14,%R9,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x4,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R8,%R9 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 427010 <advec_cell_kernel_module_mp_advec_cell_kernel_.DIR.OMP.PARALLEL.2+0x13b0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
