| Loop Id: 238 | Module: exec | Source: field_summary_kernel.f90:58-71 | Coverage: 0.29% |
|---|
| Loop Id: 238 | Module: exec | Source: field_summary_kernel.f90:58-71 | Coverage: 0.29% |
|---|
0x43cc70 VMOVDQA %XMM14,%XMM15 |
0x43cc75 VPADDQ %XMM8,%XMM14,%XMM15 |
0x43cc7a VMOVQ %XMM15,%RCX |
0x43cc7f SUB %R15,%RCX |
0x43cc82 VMOVUPD (%R14,%RCX,8),%ZMM15 [1] |
0x43cc89 VMOVUPD 0x8(%R14,%RCX,8),%ZMM16 [1] |
0x43cc94 VMOVUPD (%R8,%RCX,8),%ZMM17 [3] |
0x43cc9b VMOVUPD 0x8(%R8,%RCX,8),%ZMM18 [3] |
0x43cca6 VMOVUPD (%RDI,%RCX,8),%ZMM19 [7] |
0x43ccad VMOVUPD 0x8(%RDI,%RCX,8),%ZMM20 [7] |
0x43ccb8 VMOVUPD (%R9,%RCX,8),%ZMM21 [4] |
0x43ccbf VMOVUPD (%R10,%RCX,8),%ZMM22 [6] |
0x43ccc6 VMULPD (%R12,%RCX,8),%ZMM22,%ZMM23 [5] |
0x43cccd VFMADD231PD (%RAX,%RCX,8),%ZMM23,%ZMM11 [8] |
0x43ccd4 VMOVUPD 0x8(%R9,%RCX,8),%ZMM24 [4] |
0x43ccdf VFMADD231PD (%RBX,%RCX,8),%ZMM22,%ZMM13 [2] |
0x43cce6 VMULPD %ZMM15,%ZMM15,%ZMM15 |
0x43ccec VFMADD213PD %ZMM15,%ZMM17,%ZMM17 |
0x43ccf2 VFMADD231PD %ZMM16,%ZMM16,%ZMM17 |
0x43ccf8 VFMADD231PD %ZMM18,%ZMM18,%ZMM17 |
0x43ccfe VFMADD213PD %ZMM17,%ZMM19,%ZMM19 |
0x43cd04 VFMADD213PD %ZMM19,%ZMM21,%ZMM21 |
0x43cd0a VFMADD231PD %ZMM20,%ZMM20,%ZMM21 |
0x43cd10 VFMADD231PD %ZMM24,%ZMM24,%ZMM21 |
0x43cd16 VADDPD %ZMM22,%ZMM9,%ZMM9 |
0x43cd1c VADDPD %ZMM23,%ZMM10,%ZMM10 |
0x43cd22 VMULPD %ZMM21,%ZMM23,%ZMM15 |
0x43cd28 VFMADD231PD %ZMM7,%ZMM15,%ZMM12 |
0x43cd2e VPADDQ %ZMM6,%ZMM14,%ZMM14 |
0x43cd34 ADD $0x8,%R13 |
0x43cd38 CMP %RDX,%R13 |
0x43cd3b JB 43cc70 |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 58 - 71 |
-------------------------------------------------------------------------------- |
58: DO j=x_min,x_max |
59: vsqrd=0.0 |
60: DO kv=k,k+1 |
61: DO jv=j,j+1 |
62: vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2) |
63: ENDDO |
64: ENDDO |
65: cell_vol=volume(j,k) |
66: cell_mass=cell_vol*density0(j,k) |
67: vol=vol+cell_vol |
68: mass=mass+cell_mass |
69: ie=ie+cell_mass*energy0(j,k) |
70: ke=ke+cell_mass*0.5*vsqrd |
71: press=press+cell_vol*pressure(j,k) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.13 |
| Bottlenecks | P0, P5, |
| Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
| Source | field_summary_kernel.f90:58-71 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.50 |
| CQA cycles if no scalar integer | 8.50 |
| CQA cycles if FP arith vectorized | 8.50 |
| CQA cycles if fully vectorized | 8.50 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 8.50 |
| P0 cycles | 7.50 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 0.00 |
| P4 cycles | 8.50 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 4.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 10.49 |
| Stall cycles (UFS) | 4.46 |
| Nb insns | 32.00 |
| Nb uops | 31.00 |
| Nb loads | 12.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 23.53 |
| Nb FLOP add-sub | 16.00 |
| Nb FLOP mul | 24.00 |
| Nb FLOP fma | 80.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 90.35 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 768.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 8.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 96.43 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 91.52 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 81.25 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.13 |
| Bottlenecks | P0, P5, |
| Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
| Source | field_summary_kernel.f90:58-71 |
| Source loop unroll info | multi-versionned |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.50 |
| CQA cycles if no scalar integer | 8.50 |
| CQA cycles if FP arith vectorized | 8.50 |
| CQA cycles if fully vectorized | 8.50 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 8.50 |
| P0 cycles | 7.50 |
| P1 cycles | 4.00 |
| P2 cycles | 4.00 |
| P3 cycles | 0.00 |
| P4 cycles | 8.50 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 1.00 |
| P10 cycles | 4.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 4 |
| FE+BE cycles (UFS) | 10.49 |
| Stall cycles (UFS) | 4.46 |
| Nb insns | 32.00 |
| Nb uops | 31.00 |
| Nb loads | 12.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 23.53 |
| Nb FLOP add-sub | 16.00 |
| Nb FLOP mul | 24.00 |
| Nb FLOP fma | 80.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 90.35 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 768.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 8.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 96.43 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 50.00 |
| Vector-efficiency ratio all | 91.52 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 81.25 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 18.75 |
| Path / |
| Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | field_summary_kernel.f90:58-71 |
| Module | exec |
| nb instructions | 32 |
| nb uops | 31 |
| loop length | 209 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 18 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.67 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 1.00 | 4.00 | 4.00 | 0.00 | 8.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
| cycles | 8.50 | 7.50 | 4.00 | 4.00 | 0.00 | 8.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 10.49 |
| Stall cycles | 4.46 |
| LM full (events) | 5.03 |
| Front-end | 5.67 |
| Dispatch | 8.50 |
| Data deps. | 4.00 |
| Overall L1 | 8.50 |
| all | 75% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 50% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 96% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 40% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 62% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 18% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 91% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 81% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQA %XMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDQ %XMM8,%XMM14,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVQ %XMM15,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| SUB %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMOVUPD (%R14,%RCX,8),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%R14,%RCX,8),%ZMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R8,%RCX,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%R8,%RCX,8),%ZMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RDI,%RCX,8),%ZMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%RDI,%RCX,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R9,%RCX,8),%ZMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%RCX,8),%ZMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%R12,%RCX,8),%ZMM22,%ZMM23 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%RAX,%RCX,8),%ZMM23,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x8(%R9,%RCX,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD231PD (%RBX,%RCX,8),%ZMM22,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD %ZMM15,%ZMM15,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM15,%ZMM17,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM16,%ZMM16,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM18,%ZMM18,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM17,%ZMM19,%ZMM19 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM19,%ZMM21,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM20,%ZMM20,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM24,%ZMM24,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDPD %ZMM22,%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM23,%ZMM10,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM21,%ZMM23,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM7,%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPADDQ %ZMM6,%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADD $0x8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RDX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 43cc70 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | field_summary_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | field_summary_kernel.f90:58-71 |
| Module | exec |
| nb instructions | 32 |
| nb uops | 31 |
| loop length | 209 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 18 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.67 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.50 | 1.00 | 4.00 | 4.00 | 0.00 | 8.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
| cycles | 8.50 | 7.50 | 4.00 | 4.00 | 0.00 | 8.50 | 1.00 | 0.00 | 0.00 | 0.00 | 1.00 | 4.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 4.00 |
| FE+BE cycles | 10.49 |
| Stall cycles | 4.46 |
| LM full (events) | 5.03 |
| Front-end | 5.67 |
| Dispatch | 8.50 |
| Data deps. | 4.00 |
| Overall L1 | 8.50 |
| all | 75% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 50% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 96% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 40% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 62% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 18% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 91% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 81% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVDQA %XMM14,%XMM15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDQ %XMM8,%XMM14,%XMM15 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVQ %XMM15,%RCX | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| SUB %R15,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMOVUPD (%R14,%RCX,8),%ZMM15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%R14,%RCX,8),%ZMM16 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R8,%RCX,8),%ZMM17 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%R8,%RCX,8),%ZMM18 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RDI,%RCX,8),%ZMM19 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x8(%RDI,%RCX,8),%ZMM20 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R9,%RCX,8),%ZMM21 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%R10,%RCX,8),%ZMM22 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMULPD (%R12,%RCX,8),%ZMM22,%ZMM23 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VFMADD231PD (%RAX,%RCX,8),%ZMM23,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD 0x8(%R9,%RCX,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFMADD231PD (%RBX,%RCX,8),%ZMM22,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD %ZMM15,%ZMM15,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM15,%ZMM17,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM16,%ZMM16,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM18,%ZMM18,%ZMM17 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM17,%ZMM19,%ZMM19 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM19,%ZMM21,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM20,%ZMM20,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM24,%ZMM24,%ZMM21 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDPD %ZMM22,%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM23,%ZMM10,%ZMM10 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM21,%ZMM23,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD231PD %ZMM7,%ZMM15,%ZMM12 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VPADDQ %ZMM6,%ZMM14,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADD $0x8,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RDX,%R13 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 43cc70 <field_summary_kernel_module_mp_field_summary_kernel_.DIR.OMP.PARALLEL.2+0x440> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
