| Loop Id: 11 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 6.42% |
|---|
| Loop Id: 11 | Module: exec | Source: PdV_kernel.f90:114-135 [...] | Coverage: 6.42% |
|---|
0x406600 MOV 0x430(%RSP),%RDX [27] |
0x406608 VMOVUPD (%RDX,%RAX,1),%ZMM1 [12] |
0x40660f MOV 0x420(%RSP),%RDX [27] |
0x406617 VMOVUPD (%RDX,%RAX,1),%ZMM3 [29] |
0x40661e MOV 0x418(%RSP),%RDX [27] |
0x406626 VADDPD (%R12,%RAX,1),%ZMM1,%ZMM2 [20] |
0x40662d VMOVUPD (%R11,%RAX,1),%ZMM1 [7] |
0x406634 VMOVUPD (%RDX,%RAX,1),%ZMM8 [21] |
0x40663b MOV 0x410(%RSP),%RDX [27] |
0x406643 VADDPD (%R9,%RAX,1),%ZMM3,%ZMM0 [9] |
0x40664a VMOVUPD (%RDX,%RAX,1),%ZMM12 [10] |
0x406651 VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM11 [18] |
0x406658 MOV 0x3f8(%RSP),%RDX [27] |
0x406660 VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM13 [19] |
0x406667 VADDPD %ZMM0,%ZMM2,%ZMM9 |
0x40666d VADDPD (%R10,%RAX,1),%ZMM1,%ZMM2 [15] |
0x406674 VADDPD %ZMM13,%ZMM11,%ZMM14 |
0x40667a VMULPD (%RDX,%RAX,1),%ZMM14,%ZMM15 [11] |
0x406681 MOV 0x3c8(%RSP),%RDX [27] |
0x406689 VMOVUPD (%RDX,%RAX,1),%ZMM3 [23] |
0x406690 MOV 0x408(%RSP),%RDX [27] |
0x406698 VMOVUPD (%RDX,%RAX,1),%ZMM8 [3] |
0x40669f MOV 0x400(%RSP),%RDX [27] |
0x4066a7 VADDPD (%R8,%RAX,1),%ZMM3,%ZMM0 [28] |
0x4066ae VMOVUPD (%RDX,%RAX,1),%ZMM12 [25] |
0x4066b5 MOV 0x3c0(%RSP),%RDX [27] |
0x4066bd VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 [16] |
0x4066c4 VADDPD (%RDX,%RAX,1),%ZMM12,%ZMM14 [13] |
0x4066cb MOV 0x3f0(%RSP),%RDX [27] |
0x4066d3 VADDPD %ZMM0,%ZMM2,%ZMM11 |
0x4066d9 VADDPD %ZMM14,%ZMM13,%ZMM1 |
0x4066df VMULPD (%RDX,%RAX,1),%ZMM1,%ZMM2 [4] |
0x4066e6 MOV 0x428(%RSP),%RDX [27] |
0x4066ee VFMADD132PD (%RDX,%RAX,1),%ZMM15,%ZMM9 [6] |
0x4066f5 MOV 0x438(%RSP),%RDX [27] |
0x4066fd VFMADD132PD (%RBX,%RAX,1),%ZMM2,%ZMM11 [24] |
0x406704 VMULSD (%RDX),%XMM4,%XMM15 [1] |
0x406708 MOV 0x3e8(%RSP),%RDX [27] |
0x406710 VMOVUPD (%RDX,%RAX,1),%ZMM12 [26] |
0x406717 MOV 0x3e0(%RSP),%RDX [27] |
0x40671f VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 [22] |
0x406726 VSUBPD %ZMM9,%ZMM11,%ZMM9 |
0x40672c VMOVUPD (%R14,%RAX,1),%ZMM11 [5] |
0x406733 VBROADCASTSD %XMM15,%ZMM3 |
0x406739 VDIVPD %ZMM11,%ZMM5,%ZMM2 |
0x40673f VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM1 [14] |
0x406747 VMULPD %ZMM3,%ZMM9,%ZMM0 |
0x40674d VMULPD %ZMM2,%ZMM1,%ZMM15 |
0x406753 VADDPD %ZMM11,%ZMM0,%ZMM8 |
0x406759 VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM0 [17] |
0x406760 MOV 0x3d8(%RSP),%RDX [27] |
0x406768 VDIVPD %ZMM8,%ZMM11,%ZMM13 |
0x40676e VMOVUPD %ZMM0,(%RDX,%RAX,1) [8] |
0x406775 MOV 0x3d0(%RSP),%RDX [27] |
0x40677d VMULPD (%R13,%RAX,1),%ZMM13,%ZMM9 [14] |
0x406785 VMOVUPD %ZMM9,(%RDX,%RAX,1) [2] |
0x40678c MOV 0x3b0(%RSP),%RDX [27] |
0x406794 ADD $0x40,%RAX |
0x406798 CMP %RDX,%RAX |
0x40679b JNE 406600 |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135 |
-------------------------------------------------------------------------------- |
114: +xvel1(j ,k )+xvel1(j ,k+1)))*0.25_8*dt |
115: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
116: +xvel1(j+1,k )+xvel1(j+1,k+1)))*0.25_8*dt |
117: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
118: +yvel1(j ,k )+yvel1(j+1,k )))*0.25_8*dt |
119: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
120: +yvel1(j ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt |
121: total_flux=right_flux-left_flux+top_flux-bottom_flux |
122: |
123: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
129: recip_volume=1.0/volume(j,k) |
130: |
131: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
132: |
133: energy1(j,k)=energy0(j,k)-energy_change |
134: |
135: density1(j,k)=density0(j,k)*volume_change_s |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○98.22 | gomp_thread_start | team.c:130 | libgomp.so.1.0.0 |
| ○1.78 | GOMP_parallel | libgomp.h:985 | libgomp.so.1.0.0 |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.91 |
| Bottlenecks | P0, |
| Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:114-123,PdV_kernel.f90:129-135 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 48.00 |
| CQA cycles if no scalar integer | 48.00 |
| CQA cycles if FP arith vectorized | 48.00 |
| CQA cycles if fully vectorized | 48.00 |
| Front-end cycles | 13.50 |
| DIV/SQRT cycles | 16.50 |
| P0 cycles | 12.00 |
| P1 cycles | 14.67 |
| P2 cycles | 14.67 |
| P3 cycles | 1.00 |
| P4 cycles | 16.50 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 14.67 |
| P11 cycles | 48.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 48.37 - 49.19 |
| Stall cycles (UFS) | 34.29 - 35.11 |
| Nb insns | 60.00 |
| Nb uops | 66.00 |
| Nb loads | 44.00 |
| Nb stores | 2.00 |
| Nb stack references | 17.00 |
| FLOP/cycle | 4.85 |
| Nb FLOP add-sub | 120.00 |
| Nb FLOP mul | 41.00 |
| Nb FLOP fma | 24.00 |
| Nb FLOP div | 24.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 40.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1808.00 |
| Bytes stored | 128.00 |
| Stride 0 | 1.00 |
| Stride 1 | 11.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 95.00 |
| Vectorization ratio load | 96.30 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 83.33 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 95.63 |
| Vector-efficiency ratio load | 96.76 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 85.42 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 12.50 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.91 |
| Bottlenecks | P0, |
| Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:114-123,PdV_kernel.f90:129-135 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 48.00 |
| CQA cycles if no scalar integer | 48.00 |
| CQA cycles if FP arith vectorized | 48.00 |
| CQA cycles if fully vectorized | 48.00 |
| Front-end cycles | 13.50 |
| DIV/SQRT cycles | 16.50 |
| P0 cycles | 12.00 |
| P1 cycles | 14.67 |
| P2 cycles | 14.67 |
| P3 cycles | 1.00 |
| P4 cycles | 16.50 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 0.00 |
| P10 cycles | 14.67 |
| P11 cycles | 48.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 48.37 - 49.19 |
| Stall cycles (UFS) | 34.29 - 35.11 |
| Nb insns | 60.00 |
| Nb uops | 66.00 |
| Nb loads | 44.00 |
| Nb stores | 2.00 |
| Nb stack references | 17.00 |
| FLOP/cycle | 4.85 |
| Nb FLOP add-sub | 120.00 |
| Nb FLOP mul | 41.00 |
| Nb FLOP fma | 24.00 |
| Nb FLOP div | 24.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 40.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 1808.00 |
| Bytes stored | 128.00 |
| Stride 0 | 1.00 |
| Stride 1 | 11.00 |
| Stride n | 1.00 |
| Stride unknown | 1.00 |
| Stride indirect | 1.00 |
| Vectorization ratio all | 95.00 |
| Vectorization ratio load | 96.30 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 83.33 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 95.63 |
| Vector-efficiency ratio load | 96.76 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 85.42 |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:114-135 |
| Module | exec |
| nb instructions | 60 |
| nb uops | 66 |
| loop length | 417 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 12 |
| nb stack references | 17 |
| ADD-SUB / MUL ratio | 2.50 |
| micro-operation queue | 13.50 cycles |
| front end | 13.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 16.50 | 1.00 | 14.67 | 14.67 | 1.00 | 16.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 14.67 |
| cycles | 16.50 | 12.00 | 14.67 | 14.67 | 1.00 | 16.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 14.67 |
| Cycles executing div or sqrt instructions | 48.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 48.37-49.19 |
| Stall cycles | 34.29-35.11 |
| LB full (events) | 36.60-37.44 |
| LM full (events) | 1.29-1.25 |
| Front-end | 13.50 |
| Dispatch | 16.50 |
| DIV/SQRT | 48.00 |
| Data deps. | 1.00 |
| Overall L1 | 48.00 |
| all | 95% |
| load | 96% |
| store | 100% |
| mul | 83% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 0% |
| all | 95% |
| load | 96% |
| store | 100% |
| mul | 85% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x430(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x420(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x418(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R12,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x410(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R9,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x3f8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM0,%ZMM2,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD (%R10,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM13,%ZMM11,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD (%RDX,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3c8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x408(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x400(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R8,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x3c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RDX,%RAX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x3f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %ZMM0,%ZMM2,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM14,%ZMM13,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD (%RDX,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x428(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD (%RDX,%RAX,1),%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x438(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM2,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD (%RDX),%XMM4,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3e8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x3e0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD %ZMM9,%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R14,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VBROADCASTSD %XMM15,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVPD %ZMM11,%ZMM5,%ZMM2 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM1 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
| VMULPD %ZMM3,%ZMM9,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM2,%ZMM1,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDPD %ZMM11,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3d8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VDIVPD %ZMM8,%ZMM11,%ZMM13 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD %ZMM0,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| MOV 0x3d0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R13,%RAX,1),%ZMM13,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM9,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| MOV 0x3b0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 406600 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1df0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | __pdv_kernel_module_MOD_pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:114-135 |
| Module | exec |
| nb instructions | 60 |
| nb uops | 66 |
| loop length | 417 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 0 |
| used zmm registers | 12 |
| nb stack references | 17 |
| ADD-SUB / MUL ratio | 2.50 |
| micro-operation queue | 13.50 cycles |
| front end | 13.50 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 16.50 | 1.00 | 14.67 | 14.67 | 1.00 | 16.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 14.67 |
| cycles | 16.50 | 12.00 | 14.67 | 14.67 | 1.00 | 16.50 | 1.00 | 1.00 | 1.00 | 1.00 | 0.00 | 14.67 |
| Cycles executing div or sqrt instructions | 48.00 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 48.37-49.19 |
| Stall cycles | 34.29-35.11 |
| LB full (events) | 36.60-37.44 |
| LM full (events) | 1.29-1.25 |
| Front-end | 13.50 |
| Dispatch | 16.50 |
| DIV/SQRT | 48.00 |
| Data deps. | 1.00 |
| Overall L1 | 48.00 |
| all | 95% |
| load | 96% |
| store | 100% |
| mul | 83% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 0% |
| all | 95% |
| load | 96% |
| store | 100% |
| mul | 85% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 12% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV 0x430(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x420(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x418(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R12,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%R11,%RAX,1),%ZMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x410(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R9,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VADDPD (%RDI,%RAX,1),%ZMM8,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x3f8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%RSI,%RAX,1),%ZMM12,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM0,%ZMM2,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD (%R10,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD %ZMM13,%ZMM11,%ZMM14 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD (%RDX,%RAX,1),%ZMM14,%ZMM15 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3c8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x408(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x400(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R8,%RAX,1),%ZMM3,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x3c0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%RCX,%RAX,1),%ZMM8,%ZMM13 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VADDPD (%RDX,%RAX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| MOV 0x3f0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD %ZMM0,%ZMM2,%ZMM11 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM14,%ZMM13,%ZMM1 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD (%RDX,%RAX,1),%ZMM1,%ZMM2 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x428(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD (%RDX,%RAX,1),%ZMM15,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x438(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD132PD (%RBX,%RAX,1),%ZMM2,%ZMM11 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD (%RDX),%XMM4,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3e8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVUPD (%RDX,%RAX,1),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| MOV 0x3e0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDPD (%R15,%RAX,1),%ZMM12,%ZMM14 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.65 |
| VSUBPD %ZMM9,%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD (%R14,%RAX,1),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VBROADCASTSD %XMM15,%ZMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VDIVPD %ZMM11,%ZMM5,%ZMM2 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VDIVPD (%R13,%RAX,1),%ZMM14,%ZMM1 | 4 | 2.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 22-24 | 16 |
| VMULPD %ZMM3,%ZMM9,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM2,%ZMM1,%ZMM15 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDPD %ZMM11,%ZMM0,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFNMADD213PD (%RDX,%RAX,1),%ZMM15,%ZMM0 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| MOV 0x3d8(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VDIVPD %ZMM8,%ZMM11,%ZMM13 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VMOVUPD %ZMM0,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| MOV 0x3d0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULPD (%R13,%RAX,1),%ZMM13,%ZMM9 | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %ZMM9,(%RDX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| MOV 0x3b0(%RSP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| ADD $0x40,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %RDX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 406600 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x1df0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
