| Loop Id: 171 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 3.77% |
|---|
| Loop Id: 171 | Module: exec | Source: advec_mom_kernel.f90:81-177 [...] | Coverage: 3.77% |
|---|
0x435980 VCMPPD $0x1,%ZMM28,%ZMM11,%K1 |
0x435987 VMOVAPD %ZMM7,%ZMM0{%K1}{z} |
0x43598d VSUBPD %ZMM26,%ZMM9,%ZMM5 |
0x435993 VFMADD213PD %ZMM25,%ZMM0,%ZMM5 |
0x435999 VMULPD %ZMM24,%ZMM5,%ZMM0 |
0x43599f VMOVUPD %ZMM0,(%R15,%R8,8) [7] |
0x4359a6 ADD $0x8,%R8 |
0x4359aa CMP %R10,%R8 |
0x4359ad JGE 435b40 |
0x4359b3 VMOVUPD (%R9,%R8,8),%ZMM24 [8] |
0x4359ba VFPCLASSPD $0x50,%ZMM24,%K1 |
0x4359c1 LEA (%R11,%R8,1),%R14D |
0x4359c5 VPBROADCASTD %R14D,%YMM7 |
0x4359cb VPADDD %YMM6,%YMM7,%YMM27 |
0x4359d1 VPADDD %YMM15,%YMM7,%YMM25 |
0x4359d7 VPBLENDMD %YMM25,%YMM27,%YMM28{%K1} |
0x4359dd VMOVDQA32 %YMM27,%YMM25{%K1} |
0x4359e3 VPMOVSXDQ %YMM25,%ZMM25 |
0x4359e9 VPSUBQ %ZMM4,%ZMM25,%ZMM26 |
0x4359ef KXNORW %K0,%K0,%K2 |
0x4359f3 VXORPD %XMM30,%XMM30,%XMM30 |
0x4359f9 VGATHERQPD (%R13,%ZMM26,8),%ZMM30{%K2} [1] |
0x435a01 KXNORW %K0,%K0,%K2 |
0x435a05 VPXORD %XMM25,%XMM25,%XMM25 |
0x435a0b VGATHERQPD (%R12,%ZMM26,8),%ZMM25{%K2} [6] |
0x435a12 VPADDD %YMM14,%YMM7,%YMM29 |
0x435a18 VMOVDQA64 %YMM29,%YMM26 |
0x435a1e VPADDD %YMM16,%YMM7,%YMM26{%K1} |
0x435a24 VANDPD %ZMM8,%ZMM24,%ZMM7 |
0x435a2a VPMOVSXDQ %YMM26,%ZMM26 |
0x435a30 VPSUBQ %ZMM4,%ZMM26,%ZMM26 |
0x435a36 KXNORW %K0,%K0,%K2 |
0x435a3a VXORPD %XMM31,%XMM31,%XMM31 |
0x435a40 VGATHERQPD (%R12,%ZMM26,8),%ZMM31{%K2} [2] |
0x435a47 VDIVPD %ZMM30,%ZMM7,%ZMM26 |
0x435a4d VPMOVSXDQ %YMM28,%ZMM7 |
0x435a53 VPSUBQ %ZMM4,%ZMM7,%ZMM7 |
0x435a59 KXNORW %K0,%K0,%K2 |
0x435a5d VPXORD %XMM28,%XMM28,%XMM28 |
0x435a63 VGATHERQPD (%R12,%ZMM7,8),%ZMM28{%K2} [5] |
0x435a6a VXORPD %XMM7,%XMM7,%XMM7 |
0x435a6e VSUBPD %ZMM31,%ZMM25,%ZMM31 |
0x435a74 VSUBPD %ZMM25,%ZMM28,%ZMM30 |
0x435a7a VMULPD %ZMM31,%ZMM30,%ZMM28 |
0x435a80 VCMPPD $0x1,%ZMM28,%ZMM7,%K0 |
0x435a87 KORTESTB %K0,%K0 |
0x435a8b JE 435980 |
0x435a91 VCMPPD $0x1,%ZMM28,%ZMM11,%K2 |
0x435a98 VMOVDQA32 %YMM27,%YMM29{%K1} |
0x435a9e VMOVUPD (%RDI,%R8,8),%ZMM7{%K2}{z} [3] |
0x435aa5 VANDPD %ZMM8,%ZMM30,%ZMM27 |
0x435aab VSUBPD %ZMM26,%ZMM10,%ZMM5 |
0x435ab1 VMULPD %ZMM5,%ZMM27,%ZMM5 |
0x435ab7 VDIVPD %ZMM7,%ZMM5,%ZMM5 |
0x435abd VPMOVSXDQ %YMM29,%ZMM29 |
0x435ac3 VPSUBQ %ZMM4,%ZMM29,%ZMM29 |
0x435ac9 VPXOR %XMM0,%XMM0,%XMM0 |
0x435acd MOV 0x80(%RSP),%R14 [4] |
0x435ad5 VGATHERQPD (%R14,%ZMM29,8),%ZMM0{%K2} [9] |
0x435adc VANDPD %ZMM8,%ZMM31,%ZMM29 |
0x435ae2 VMINPD %ZMM27,%ZMM29,%ZMM27 |
0x435ae8 VFMADD213PD %ZMM29,%ZMM26,%ZMM29 |
0x435aee VDIVPD %ZMM0,%ZMM29,%ZMM0 |
0x435af4 VADDPD %ZMM5,%ZMM0,%ZMM0 |
0x435afa VMULPD %ZMM12,%ZMM7,%ZMM5 |
0x435b00 VMULPD %ZMM0,%ZMM5,%ZMM0 |
0x435b06 VMINPD %ZMM27,%ZMM0,%ZMM7 |
0x435b0c VFPCLASSPD $0x56,%ZMM30,%K1 |
0x435b13 VXORPD %ZMM13,%ZMM7,%ZMM7{%K1} |
0x435b19 JMP 435980 |
/scratch_na/users/xoserete/qaas_runs/171-415-7919/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 81 - 177 |
-------------------------------------------------------------------------------- |
81: IF(mom_sweep.EQ.1)THEN ! x 1 |
[...] |
152: IF(node_flux(j,k).LT.0.0)THEN |
[...] |
158: upwind=j-1 |
159: donor=j |
160: downwind=j+1 |
161: dif=upwind |
162: ENDIF |
163: sigma=ABS(node_flux(j,k))/(node_mass_pre(donor,k)) |
164: width=celldx(j) |
165: vdiffuw=vel1(donor,k)-vel1(upwind,k) |
166: vdiffdw=vel1(downwind,k)-vel1(donor,k) |
167: limiter=0.0 |
168: IF(vdiffuw*vdiffdw.GT.0.0)THEN |
169: auw=ABS(vdiffuw) |
170: adw=ABS(vdiffdw) |
171: wind=1.0_8 |
172: IF(vdiffdw.LE.0.0) wind=-1.0_8 |
173: limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldx(dif))/6.0_8,auw,adw) |
174: ENDIF |
175: advec_vel_s=vel1(donor,k)+(1.0-sigma)*limiter |
176: mom_flux(j,k)=advec_vel_s*node_flux(j,k) |
177: ENDDO |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | __kmp_invoke_microtask | libiomp5.so | |
| ○ | __kmp_invoke_task_func | libiomp5.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.04 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.01 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 33.25 |
| CQA cycles if no scalar integer | 32.00 |
| CQA cycles if FP arith vectorized | 33.25 |
| CQA cycles if fully vectorized | 33.03 |
| Front-end cycles | 13.42 |
| DIV/SQRT cycles | 24.50 |
| P0 cycles | 7.00 |
| P1 cycles | 12.67 |
| P2 cycles | 12.67 |
| P3 cycles | 0.50 |
| P4 cycles | 24.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 12.67 |
| P11 cycles | 32.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 37.10 - 116.50 |
| Stall cycles (UFS) | 24.52 - 103.76 |
| Nb insns | 58.50 |
| Nb uops | 80.50 |
| Nb loads | 6.50 |
| Nb stores | 1.00 |
| Nb stack references | 0.50 |
| FLOP/cycle | 3.01 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 28.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 16.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.80 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 388.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.50 |
| Stride 1 | 2.50 |
| Stride n | 0.50 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 97.79 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 96.06 |
| Vector-efficiency ratio all | 77.05 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 82.31 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 66.95 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.57 |
| Bottlenecks | P0, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 48.00 |
| CQA cycles if no scalar integer | 48.00 |
| CQA cycles if FP arith vectorized | 48.00 |
| CQA cycles if fully vectorized | 48.00 |
| Front-end cycles | 16.00 |
| DIV/SQRT cycles | 30.50 |
| P0 cycles | 7.00 |
| P1 cycles | 14.33 |
| P2 cycles | 14.33 |
| P3 cycles | 0.50 |
| P4 cycles | 30.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 14.33 |
| P11 cycles | 48.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 55.24 - 142.41 |
| Stall cycles (UFS) | 40.11 - 127.28 |
| Nb insns | 70.00 |
| Nb uops | 96.00 |
| Nb loads | 8.00 |
| Nb stores | 1.00 |
| Nb stack references | 1.00 |
| FLOP/cycle | 2.83 |
| Nb FLOP add-sub | 40.00 |
| Nb FLOP mul | 40.00 |
| Nb FLOP fma | 16.00 |
| Nb FLOP div | 24.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 10.83 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 456.00 |
| Bytes stored | 64.00 |
| Stride 0 | 1.00 |
| Stride 1 | 3.00 |
| Stride n | 1.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 98.28 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 96.88 |
| Vector-efficiency ratio all | 80.28 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 84.62 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 70.51 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.16 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.02 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | NA |
| Bottlenecks | P0, P5, |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source | advec_mom_kernel.f90:81-81,advec_mom_kernel.f90:152-152,advec_mom_kernel.f90:158-177 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 18.50 |
| CQA cycles if no scalar integer | 16.00 |
| CQA cycles if FP arith vectorized | 18.50 |
| CQA cycles if fully vectorized | 18.06 |
| Front-end cycles | 10.83 |
| DIV/SQRT cycles | 18.50 |
| P0 cycles | 7.00 |
| P1 cycles | 11.00 |
| P2 cycles | 11.00 |
| P3 cycles | 0.50 |
| P4 cycles | 18.50 |
| P5 cycles | 2.00 |
| P6 cycles | 0.50 |
| P7 cycles | 0.50 |
| P8 cycles | 0.50 |
| P9 cycles | 2.00 |
| P10 cycles | 11.00 |
| P11 cycles | 16.00 |
| Inter-iter dependencies cycles | 0 |
| FE+BE cycles (UFS) | 18.97 - 90.59 |
| Stall cycles (UFS) | 8.93 - 80.24 |
| Nb insns | 47.00 |
| Nb uops | 65.00 |
| Nb loads | 5.00 |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.46 |
| Nb FLOP add-sub | 24.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 8.00 |
| Nb FLOP div | 8.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.76 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 320.00 |
| Bytes stored | 64.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 3.00 |
| Vectorization ratio all | 97.30 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | 100.00 |
| Vectorization ratio other | 95.24 |
| Vector-efficiency ratio all | 73.82 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | 100.00 |
| Vector-efficiency ratio mul | 100.00 |
| Vector-efficiency ratio add_sub | 80.00 |
| Vector-efficiency ratio fma | 100.00 |
| Vector-efficiency ratio div_sqrt | 100.00 |
| Vector-efficiency ratio other | 63.39 |
| Path / |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 58.50 |
| nb uops | 80.50 |
| loop length | 343.50 |
| used x86 registers | 9 |
| used mmx registers | 0 |
| used xmm registers | 5.50 |
| used ymm registers | 10 |
| used zmm registers | 15.50 |
| nb stack references | 0.50 |
| ADD-SUB / MUL ratio | 1.25 |
| micro-operation queue | 13.42 cycles |
| front end | 13.42 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 24.50 | 7.00 | 12.67 | 12.67 | 0.50 | 24.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 12.67 |
| cycles | 24.50 | 7.00 | 12.67 | 12.67 | 0.50 | 24.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 12.67 |
| Cycles executing div or sqrt instructions | 32.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 37.11-116.50 |
| Stall cycles | 24.52-103.76 |
| RS full (events) | 9.10-1.42 |
| PRF_FLOAT full (events) | 20.98-105.61 |
| Front-end | 13.42 |
| Dispatch | 24.50 |
| DIV/SQRT | 32.00 |
| Data deps. | 0.00 |
| Overall L1 | 33.25 |
| all | 94% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 90% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 97% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 96% |
| all | 53% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 73% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 39% |
| all | 91% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 85% |
| all | 77% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 82% |
| fma | 100% |
| div/sqrt | 100% |
| other | 66% |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 70 |
| nb uops | 96 |
| loop length | 414 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 10 |
| used zmm registers | 18 |
| nb stack references | 1 |
| ADD-SUB / MUL ratio | 1.00 |
| micro-operation queue | 16.00 cycles |
| front end | 16.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 30.50 | 7.00 | 14.33 | 14.33 | 0.50 | 30.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 14.33 |
| cycles | 30.50 | 7.00 | 14.33 | 14.33 | 0.50 | 30.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 14.33 |
| Cycles executing div or sqrt instructions | 48.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 55.24-142.41 |
| Stall cycles | 40.11-127.28 |
| RS full (events) | 0.83-1.96 |
| PRF_FLOAT full (events) | 41.96-129.06 |
| Front-end | 16.00 |
| Dispatch | 30.50 |
| DIV/SQRT | 48.00 |
| Data deps. | 0.00 |
| Overall L1 | 48.00 |
| all | 95% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 91% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 98% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 96% |
| all | 54% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 75% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 40% |
| all | 94% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 88% |
| all | 80% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 84% |
| fma | 100% |
| div/sqrt | 100% |
| other | 70% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM28,%ZMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM7,%ZMM0{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM26,%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM25,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM24,%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM0,(%R15,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 435b40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3e60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%R9,%R8,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM24,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| LEA (%R11,%R8,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| VPBROADCASTD %R14D,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDD %YMM6,%YMM7,%YMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPADDD %YMM15,%YMM7,%YMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPBLENDMD %YMM25,%YMM27,%YMM28{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA32 %YMM27,%YMM25{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM25,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM25,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R13,%ZMM26,8),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM25,%XMM25,%XMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%R12,%ZMM26,8),%ZMM25{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPADDD %YMM14,%YMM7,%YMM29 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA64 %YMM29,%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDD %YMM16,%YMM7,%YMM26{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VANDPD %ZMM8,%ZMM24,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPMOVSXDQ %YMM26,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM26,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R12,%ZMM26,8),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VDIVPD %ZMM30,%ZMM7,%ZMM26 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM28,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%R12,%ZMM7,8),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM31,%ZMM25,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM25,%ZMM28,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM31,%ZMM30,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM28,%ZMM7,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 435980 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VCMPPD $0x1,%ZMM28,%ZMM11,%K2 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVDQA32 %YMM27,%YMM29{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VMOVUPD (%RDI,%R8,8),%ZMM7{%K2}{z} | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VANDPD %ZMM8,%ZMM30,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM26,%ZMM10,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM5,%ZMM27,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM7,%ZMM5,%ZMM5 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM29,%ZMM29 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM29,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| VPXOR %XMM0,%XMM0,%XMM0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV 0x80(%RSP),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VGATHERQPD (%R14,%ZMM29,8),%ZMM0{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VANDPD %ZMM8,%ZMM31,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VMINPD %ZMM27,%ZMM29,%ZMM27 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFMADD213PD %ZMM29,%ZMM26,%ZMM29 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VDIVPD %ZMM0,%ZMM29,%ZMM0 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VADDPD %ZMM5,%ZMM0,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM12,%ZMM7,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM0,%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMINPD %ZMM27,%ZMM0,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VFPCLASSPD $0x56,%ZMM30,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VXORPD %ZMM13,%ZMM7,%ZMM7{%K1} | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| JMP 435980 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3ca0> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| Function | advec_mom_kernel_.DIR.OMP.PARALLEL.2 |
| Source file and lines | advec_mom_kernel.f90:81-177 |
| Module | exec |
| nb instructions | 47 |
| nb uops | 65 |
| loop length | 273 |
| used x86 registers | 8 |
| used mmx registers | 0 |
| used xmm registers | 5 |
| used ymm registers | 10 |
| used zmm registers | 13 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 1.50 |
| micro-operation queue | 10.83 cycles |
| front end | 10.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 18.50 | 7.00 | 11.00 | 11.00 | 0.50 | 18.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 11.00 |
| cycles | 18.50 | 7.00 | 11.00 | 11.00 | 0.50 | 18.50 | 2.00 | 0.50 | 0.50 | 0.50 | 2.00 | 11.00 |
| Cycles executing div or sqrt instructions | 16.00 |
| Longest recurrence chain latency (RecMII) | 0.00 |
| FE+BE cycles | 18.97-90.59 |
| Stall cycles | 8.93-80.24 |
| RS full (events) | 17.37-0.87 |
| Front-end | 10.83 |
| Dispatch | 18.50 |
| DIV/SQRT | 16.00 |
| Data deps. | 0.00 |
| Overall L1 | 18.50 |
| all | 93% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 88% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 100% |
| all | 97% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 95% |
| all | 53% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 71% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 39% |
| all | 89% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | 100% |
| other | 81% |
| all | 73% |
| load | 100% |
| store | 100% |
| mul | 100% |
| add-sub | 80% |
| fma | 100% |
| div/sqrt | 100% |
| other | 63% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VCMPPD $0x1,%ZMM28,%ZMM11,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VMOVAPD %ZMM7,%ZMM0{%K1}{z} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VSUBPD %ZMM26,%ZMM9,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VFMADD213PD %ZMM25,%ZMM0,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMULPD %ZMM24,%ZMM5,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVUPD %ZMM0,(%R15,%R8,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 1 |
| ADD $0x8,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R10,%R8 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 435b40 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3e60> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVUPD (%R9,%R8,8),%ZMM24 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VFPCLASSPD $0x50,%ZMM24,%K1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| LEA (%R11,%R8,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| VPBROADCASTD %R14D,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDD %YMM6,%YMM7,%YMM27 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPADDD %YMM15,%YMM7,%YMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPBLENDMD %YMM25,%YMM27,%YMM28{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA32 %YMM27,%YMM25{%K1} | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPMOVSXDQ %YMM25,%ZMM25 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM25,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM30,%XMM30,%XMM30 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R13,%ZMM26,8),%ZMM30{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM25,%XMM25,%XMM25 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%R12,%ZMM26,8),%ZMM25{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VPADDD %YMM14,%YMM7,%YMM29 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVDQA64 %YMM29,%YMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.17 |
| VPADDD %YMM16,%YMM7,%YMM26{%K1} | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VANDPD %ZMM8,%ZMM24,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VPMOVSXDQ %YMM26,%ZMM26 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM26,%ZMM26 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM31,%XMM31,%XMM31 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R12,%ZMM26,8),%ZMM31{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VDIVPD %ZMM30,%ZMM7,%ZMM26 | 3 | 2.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 22-24 | 16 |
| VPMOVSXDQ %YMM28,%ZMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPSUBQ %ZMM4,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.50 |
| KXNORW %K0,%K0,%K2 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXORD %XMM28,%XMM28,%XMM28 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0-1 | 0.33 |
| VGATHERQPD (%R12,%ZMM7,8),%ZMM28{%K2} | 5 | 1 | 0 | 2.67 | 2.67 | 0 | 2 | 0 | 0 | 0 | 0 | 0 | 2.67 | 0-29 | 2.67 |
| VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VSUBPD %ZMM31,%ZMM25,%ZMM31 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM25,%ZMM28,%ZMM30 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULPD %ZMM31,%ZMM30,%ZMM28 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VCMPPD $0x1,%ZMM28,%ZMM7,%K0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| KORTESTB %K0,%K0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JE 435980 <advec_mom_kernel_mod_mp_advec_mom_kernel_.DIR.OMP.PARALLEL.2+0x3ca0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
