| Loop Id: 35 | Module: exec | Source: timestep.c:74-78 | Coverage: 0.06% |
|---|
| Loop Id: 35 | Module: exec | Source: timestep.c:74-78 | Coverage: 0.06% |
|---|
0x40b480 LDR D0, [X19] [3] |
0x40b484 LDUR D1, [X2, #504] [2] |
0x40b488 LDUR D2, [X1, #504] [1] |
0x40b48c SUBS W0, W0, #1 |
0x40b490 FMADD D0, D0, D1, D2 |
0x40b494 LDP D2, D3, [X1] [1] |
0x40b498 STUR D0, [X1, #504] [1] |
0x40b49c LDR D0, [X19] [3] |
0x40b4a0 LDR D1, [X2] [2] |
0x40b4a4 FMADD D0, D0, D1, D2 |
0x40b4a8 STR D0, [X1] [1] |
0x40b4ac LDR D0, [X19] [3] |
0x40b4b0 LDR D1, [X2, #8] [2] |
0x40b4b4 ADD X2, X2, #24 |
0x40b4b8 FMADD D0, D0, D1, D3 |
0x40b4bc STR D0, [X1, #8] [1] |
0x40b4c0 ADD X1, X1, #24 |
0x40b4c4 B.NE 40b480 |
/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 74 - 78 |
-------------------------------------------------------------------------------- |
74: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
75: { |
76: s->atoms->p[iOff][0] += dt*s->atoms->f[iOff][0]; |
77: s->atoms->p[iOff][1] += dt*s->atoms->f[iOff][1]; |
78: s->atoms->p[iOff][2] += dt*s->atoms->f[iOff][2]; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | __kmp_invoke_microtask | libomp.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 3.68 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P10, |
| Function | .omp_outlined.#0x40b270 |
| Source | timestep.c:74-78 |
| Source loop unroll info | unrolled by 9 |
| Source loop unroll confidence level | low |
| Unroll/vectorization loop type | NA |
| Unroll factor | 9 |
| CQA cycles | 3.83 |
| CQA cycles if no scalar integer | 3.83 |
| CQA cycles if FP arith vectorized | 3.83 |
| CQA cycles if fully vectorized | 1.04 |
| Front-end cycles | 2.25 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.75 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 1.50 |
| P6 cycles | 1.50 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 3.83 |
| P10 cycles | 3.50 |
| P11 cycles | 3.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.57 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 3.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 25.04 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 72.00 |
| Bytes stored | 24.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 8.33 |
| Vectorization ratio load | 12.50 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 26.04 |
| Vector-efficiency ratio load | 28.13 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 3.68 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P10, |
| Function | .omp_outlined.#0x40b270 |
| Source | timestep.c:74-78 |
| Source loop unroll info | unrolled by 9 |
| Source loop unroll confidence level | low |
| Unroll/vectorization loop type | NA |
| Unroll factor | 9 |
| CQA cycles | 3.83 |
| CQA cycles if no scalar integer | 3.83 |
| CQA cycles if FP arith vectorized | 3.83 |
| CQA cycles if fully vectorized | 1.04 |
| Front-end cycles | 2.25 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 0.75 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 1.50 |
| P6 cycles | 1.50 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 3.83 |
| P10 cycles | 3.50 |
| P11 cycles | 3.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.57 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 3.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 25.04 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 72.00 |
| Bytes stored | 24.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 8.33 |
| Vectorization ratio load | 12.50 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 26.04 |
| Vector-efficiency ratio load | 28.13 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | .omp_outlined.#0x40b270 |
| Source file and lines | timestep.c:74-78 |
| Module | exec |
| nb instructions | 18 |
| loop length | 72 |
| nb stack references | 0 |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 3.83 | 3.50 | 3.67 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 3.83 | 3.50 | 3.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.25 |
| Data deps. | 1.00 |
| Overall L1 | 3.83 |
| all | 8% |
| load | 12% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR D1, [X2, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR D2, [X1, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| SUBS W0, W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| FMADD D0, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| LDP D2, D3, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| STUR D0, [X1, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D1, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D0, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D1, [X2, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| ADD X2, X2, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMADD D0, D0, D1, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [X1, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| ADD X1, X1, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B.NE 40b480 <.omp_outlined.+0x210> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | .omp_outlined.#0x40b270 |
| Source file and lines | timestep.c:74-78 |
| Module | exec |
| nb instructions | 18 |
| loop length | 72 |
| nb stack references | 0 |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 3.83 | 3.50 | 3.67 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 3.83 | 3.50 | 3.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.25 |
| Data deps. | 1.00 |
| Overall L1 | 3.83 |
| all | 8% |
| load | 12% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR D1, [X2, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR D2, [X1, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| SUBS W0, W0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| FMADD D0, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| LDP D2, D3, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| STUR D0, [X1, #504] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D1, [X2] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D0, D0, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D0, [X19] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D1, [X2, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| ADD X2, X2, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMADD D0, D0, D1, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [X1, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| ADD X1, X1, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B.NE 40b480 <.omp_outlined.+0x210> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
