| Loop Id: 142 | Module: exec | Source: timestep.c:110-116 | Coverage: 0.01% |
|---|
| Loop Id: 142 | Module: exec | Source: timestep.c:110-116 | Coverage: 0.01% |
|---|
0x40b7e4 LDRSW X16, [X15], #4 [1] |
0x40b7e8 LDP D3, D4, [X14, #1008] [4] |
0x40b7ec SUBS W12, W12, #1 |
0x40b7f0 ADD X16, X13, X16,LSL #4 |
0x40b7f4 FMUL D4, D4, D4 |
0x40b7f8 LDR D2, [X16, #8] [2] |
0x40b7fc FMADD D3, D3, D3, D4 |
0x40b800 FDIV D2, D1, D2 |
0x40b804 LDR D4, [X14], #24 [4] |
0x40b808 FMADD D3, D4, D4, D3 |
0x40b80c FMADD D0, D3, D2, D0 |
0x40b810 STR D0, [SP, #16] [3] |
0x40b814 B.NE 40b7e4 |
/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/timestep.c: 110 - 116 |
-------------------------------------------------------------------------------- |
110: for (int iOff=MAXATOMS*iBox,ii=0; ii<s->boxes->nAtoms[iBox]; ii++,iOff++) |
111: { |
112: int iSpecies = s->atoms->iSpecies[iOff]; |
113: real_t invMass = 0.5/s->species[iSpecies].mass; |
114: kenergy += ( s->atoms->p[iOff][0] * s->atoms->p[iOff][0] + |
115: s->atoms->p[iOff][1] * s->atoms->p[iOff][1] + |
116: s->atoms->p[iOff][2] * s->atoms->p[iOff][2] )*invMass; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | __kmp_invoke_microtask | libomp.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.00 - 4.36 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | |
| Function | .omp_outlined..4 |
| Source | timestep.c:110-116 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 0.50 - 0.46 |
| Front-end cycles | 1.63 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.50 |
| P6 cycles | 1.50 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 1.83 |
| P10 cycles | 1.50 |
| P11 cycles | 1.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 1.00 - 0.50 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 13.00 |
| Nb uops | 13.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 3.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 36.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 20.00 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 27.50 |
| Vector-efficiency ratio load | 33.33 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.00 - 4.36 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.09 |
| Bottlenecks | |
| Function | .omp_outlined..4 |
| Source | timestep.c:110-116 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.00 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 2.00 |
| CQA cycles if fully vectorized | 0.50 - 0.46 |
| Front-end cycles | 1.63 |
| DIV/SQRT cycles | 0.50 |
| P0 cycles | 0.50 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 1.50 |
| P6 cycles | 1.50 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 1.83 |
| P10 cycles | 1.50 |
| P11 cycles | 1.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 1.00 - 0.50 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 13.00 |
| Nb uops | 13.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 1.00 |
| Nb FLOP fma | 3.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 36.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 20.00 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 27.50 |
| Vector-efficiency ratio load | 33.33 |
| Vector-efficiency ratio store | 25.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | .omp_outlined..4 |
| Source file and lines | timestep.c:110-116 |
| Module | exec |
| nb instructions | 13 |
| loop length | 52 |
| nb stack references | 0 |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 1.63 |
| Data deps. | 2.00 |
| Overall L1 | 2.00 |
| all | 20% |
| load | 33% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDRSW X16, [X15], #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP D3, D4, [X14, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| SUBS W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X16, X13, X16,LSL #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMUL D4, D4, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| LDR D2, [X16, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D3, D3, D3, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FDIV D2, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1-0.50 |
| LDR D4, [X14], #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D3, D4, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FMADD D0, D3, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| B.NE 40b7e4 <.omp_outlined..4+0x174> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | .omp_outlined..4 |
| Source file and lines | timestep.c:110-116 |
| Module | exec |
| nb instructions | 13 |
| loop length | 52 |
| nb stack references | 0 |
| front end | 1.63 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| cycles | 0.50 | 0.50 | 1.00 | 1.00 | 1.00 | 1.00 | 1.50 | 1.50 | 1.50 | 1.50 | 1.83 | 1.50 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 1.63 |
| Data deps. | 2.00 |
| Overall L1 | 2.00 |
| all | 20% |
| load | 33% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDRSW X16, [X15], #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDP D3, D4, [X14, #1008] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| SUBS W12, W12, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X16, X13, X16,LSL #4 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| FMUL D4, D4, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| LDR D2, [X16, #8] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D3, D3, D3, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FDIV D2, D1, D2 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1-0.50 |
| LDR D4, [X14], #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D3, D4, D4, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FMADD D0, D3, D2, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR D0, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| B.NE 40b7e4 <.omp_outlined..4+0x174> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
