| Loop Id: 87 | Module: exec | Source: ljForce.c:191-216 [...] | Coverage: 94.58% |
|---|
| Loop Id: 87 | Module: exec | Source: ljForce.c:191-216 [...] | Coverage: 94.58% |
|---|
0x408708 ADD X26, X26, #1 |
0x40870c ADD X7, X7, #24 |
0x408710 CMP X26, X2 |
0x408714 B.GE 4086e8 |
0x408718 LDR Q5, [X5] [1] |
0x40871c LDUR Q6, [X7, #496] [2] |
0x408720 LDR D16, [X7] [2] |
0x408724 FSUB V5.2D, V5.2D, V6.2D |
0x408728 FMUL V6.2D, V5.2D, V5.2D |
0x40872c FADDP D7, V6.2D |
0x408730 LDR D6, [X6] [9] |
0x408734 FSUB D6, D6, S16 |
0x408738 LDR D16, [X23] [8] |
0x40873c FMADD D7, D6, D6, D7 |
0x408740 FCMP D7, D16 |
0x408744 B.GT 408708 |
0x408748 FCMP D7, #0 |
0x40874c B.LE 408708 |
0x408750 FDIV D7, D0, D7 |
0x408754 LDR D16, [X22] [7] |
0x408758 LDR D18, [X21] [5] |
0x40875c LDR X27, [X18, #48] [11] |
0x408760 FMUL D17, D7, D7 |
0x408764 FMUL D16, D7, D16 |
0x408768 FMUL D7, D7, D4 |
0x40876c FMUL D16, D17, D16 |
0x408770 FNMSUB D17, D16, D16, D16 |
0x408774 FMUL D7, D7, D16 |
0x408778 FSUB D17, D17, S18 |
0x40877c LDR D18, [X27, X4,LSL #3] [6] |
0x408780 FMUL D17, D17, D1 |
0x408784 FADD D18, D17, D18 |
0x408788 STR D18, [X27, X4,LSL #3] [6] |
0x40878c LDR D18, [SP, #16] [4] |
0x408790 LDR X27, [X18, #40] [11] |
0x408794 MADD X27, X4, X13, X27 |
0x408798 FADD D17, D18, D17 |
0x40879c FMADD D18, D16, D2, D3 |
0x4087a0 LDR Q16, [X27] [10] |
0x4087a4 STR D17, [SP, #16] [4] |
0x4087a8 LDR D17, [X9] [3] |
0x4087ac FMUL D7, D7, D17 |
0x4087b0 FMUL D7, D7, D18 |
0x4087b4 FMLA V16.2D, V5.2D, V7.D[0] |
0x4087b8 LDR D5, [X27, #16] [10] |
0x4087bc FMADD D5, D7, D6, D5 |
0x4087c0 STR Q16, [X27] [10] |
0x4087c4 STR D5, [X27, #16] [10] |
0x4087c8 B 408708 |
/home/hbollore/qaas/qaas-runs/169-814-5713/intel/CoMD/build/CoMD/CoMD/src-openmp/ljForce.c: 191 - 216 |
-------------------------------------------------------------------------------- |
191: for (int jOff=jBox*MAXATOMS; jOff<(jBox*MAXATOMS+nJBox); jOff++) |
[...] |
197: dr[m] = s->atoms->r[iOff][m]-s->atoms->r[jOff][m]; |
198: r2+=dr[m]*dr[m]; |
199: } |
200: |
201: if ( r2 <= rCut2 && r2 > 0.0) |
202: { |
203: |
204: // Important note: |
205: // from this point on r actually refers to 1.0/r |
206: r2 = 1.0/r2; |
207: real_t r6 = s6 * (r2*r2*r2); |
208: real_t eLocal = r6 * (r6 - 1.0) - eShift; |
209: s->atoms->U[iOff] += 0.5*eLocal; |
210: ePot += 0.5*eLocal; |
211: |
212: // different formulation to avoid sqrt computation |
213: real_t fr = - 4.0*epsilon*r6*r2*(12.0*r6 - 6.0); |
214: for (int m=0; m<3; m++) |
215: { |
216: s->atoms->f[iOff][m] -= dr[m]*fr; |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ○100.00 | __kmp_invoke_microtask | libomp.so |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.22 |
| CQA speedup if FP arith vectorized | 1.22 |
| CQA speedup if fully vectorized | 3.38 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.12 |
| Bottlenecks | |
| Function | .omp_outlined..5#0x408580 |
| Source | ljForce.c:191-191,ljForce.c:197-216 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.67 |
| CQA cycles if no scalar integer | 3.00 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 1.08 |
| Front-end cycles | 3.46 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 0.83 |
| P2 cycles | 0.83 |
| P3 cycles | 0.83 |
| P4 cycles | 0.83 |
| P5 cycles | 3.42 |
| P6 cycles | 3.33 |
| P7 cycles | 3.33 |
| P8 cycles | 3.25 |
| P9 cycles | 3.11 |
| P10 cycles | 3.11 |
| P11 cycles | 3.11 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.33 - 0.17 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 27.67 |
| Nb uops | 27.67 |
| Nb loads | NA |
| Nb stores | 1.33 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.18 |
| Nb FLOP add-sub | 5.00 |
| Nb FLOP mul | 4.67 |
| Nb FLOP fma | 2.67 |
| Nb FLOP div | 0.33 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 26.32 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 82.67 |
| Bytes stored | 13.33 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 40.74 |
| Vectorization ratio load | 35.00 |
| Vectorization ratio store | 25.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 35.19 |
| Vector-efficiency ratio load | 33.75 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 37.50 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.20 |
| CQA speedup if FP arith vectorized | 1.20 |
| CQA speedup if fully vectorized | 3.20 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.20 |
| Bottlenecks | micro-operation queue, |
| Function | .omp_outlined..5#0x408580 |
| Source | ljForce.c:191-191,ljForce.c:197-216 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.00 |
| CQA cycles if no scalar integer | 1.67 |
| CQA cycles if FP arith vectorized | 1.67 |
| CQA cycles if fully vectorized | 0.63 |
| Front-end cycles | 2.00 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 0.75 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 1.50 |
| P6 cycles | 1.50 |
| P7 cycles | 1.50 |
| P8 cycles | 1.50 |
| P9 cycles | 1.67 |
| P10 cycles | 1.67 |
| P11 cycles | 1.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 16.00 |
| Nb uops | 16.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.00 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 28.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 44.44 |
| Vectorization ratio load | 40.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 36.11 |
| Vector-efficiency ratio load | 35.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 37.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.27 |
| CQA speedup if FP arith vectorized | 1.19 |
| CQA speedup if fully vectorized | 3.48 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.10 |
| Bottlenecks | P6, P7, P8, P9, |
| Function | .omp_outlined..5#0x408580 |
| Source | ljForce.c:191-191,ljForce.c:197-216 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 5.33 |
| CQA cycles if FP arith vectorized | 5.67 |
| CQA cycles if fully vectorized | 1.94 |
| Front-end cycles | 6.13 |
| DIV/SQRT cycles | 2.00 |
| P0 cycles | 2.00 |
| P1 cycles | 1.00 |
| P2 cycles | 1.00 |
| P3 cycles | 1.00 |
| P4 cycles | 1.00 |
| P5 cycles | 6.75 |
| P6 cycles | 6.75 |
| P7 cycles | 6.75 |
| P8 cycles | 6.75 |
| P9 cycles | 6.00 |
| P10 cycles | 6.00 |
| P11 cycles | 6.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 1.00 - 0.50 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 49.00 |
| Nb uops | 49.00 |
| Nb loads | NA |
| Nb stores | 4.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 4.44 |
| Nb FLOP add-sub | 7.00 |
| Nb FLOP mul | 10.00 |
| Nb FLOP fma | 6.00 |
| Nb FLOP div | 1.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 26.07 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 136.00 |
| Bytes stored | 40.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 33.33 |
| Vectorization ratio load | 25.00 |
| Vectorization ratio store | 25.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 33.33 |
| Vector-efficiency ratio load | 31.25 |
| Vector-efficiency ratio store | 31.25 |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 37.50 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.13 |
| CQA speedup if FP arith vectorized | 1.35 |
| CQA speedup if fully vectorized | 3.27 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.13 |
| Bottlenecks | micro-operation queue, |
| Function | .omp_outlined..5#0x408580 |
| Source | ljForce.c:191-191,ljForce.c:197-216 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 2.25 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 1.67 |
| CQA cycles if fully vectorized | 0.69 |
| Front-end cycles | 2.25 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 0.75 |
| P2 cycles | 0.75 |
| P3 cycles | 0.75 |
| P4 cycles | 0.75 |
| P5 cycles | 2.00 |
| P6 cycles | 1.75 |
| P7 cycles | 1.75 |
| P8 cycles | 1.50 |
| P9 cycles | 1.67 |
| P10 cycles | 1.67 |
| P11 cycles | 1.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 18.00 |
| Nb uops | 18.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.56 |
| Nb FLOP add-sub | 4.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 24.89 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 44.44 |
| Vectorization ratio load | 40.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 50.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 36.11 |
| Vector-efficiency ratio load | 35.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 50.00 |
| Vector-efficiency ratio add_sub | 37.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 25.00 |
| Path / |
| Function | .omp_outlined..5#0x408580 |
| Source file and lines | ljForce.c:191-216 |
| Module | exec |
| nb instructions | 27.67 |
| loop length | 110.67 |
| nb stack references | 0 |
| front end | 3.46 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 0.83 | 0.83 | 0.83 | 0.83 | 3.42 | 3.33 | 3.33 | 3.25 | 3.11 | 3.11 | 3.11 | 0.00 | 0.00 |
| cycles | 1.50 | 1.50 | 0.83 | 0.83 | 0.83 | 0.83 | 3.42 | 3.33 | 3.33 | 3.25 | 3.11 | 3.11 | 3.11 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 0.33-0.17 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 3.46 |
| Data deps. | 1.00 |
| Overall L1 | 3.67 |
| all | 26% |
| load | 35% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 40% |
| load | 35% |
| store | 25% |
| mul | 100% |
| add-sub | 50% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Function | .omp_outlined..5#0x408580 |
| Source file and lines | ljForce.c:191-216 |
| Module | exec |
| nb instructions | 16 |
| loop length | 64 |
| nb stack references | 0 |
| front end | 2.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 0.75 | 0.75 | 0.75 | 0.75 | 1.50 | 1.50 | 1.50 | 1.50 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.00 |
| Data deps. | 1.00 |
| Overall L1 | 2.00 |
| all | 28% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 44% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X26, X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X7, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X26, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4086e8 <.omp_outlined..5+0x168> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR Q5, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR Q6, [X7, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D16, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB V5.2D, V5.2D, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMUL V6.2D, V5.2D, V5.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FADDP D7, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D6, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB D6, D6, S16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D16, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D7, D6, D6, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FCMP D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| B.GT 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | .omp_outlined..5#0x408580 |
| Source file and lines | ljForce.c:191-216 |
| Module | exec |
| nb instructions | 49 |
| loop length | 196 |
| nb stack references | 0 |
| front end | 6.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| cycles | 2.00 | 2.00 | 1.00 | 1.00 | 1.00 | 1.00 | 6.75 | 6.75 | 6.75 | 6.75 | 6.00 | 6.00 | 6.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | 1.00-0.50 |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 6.13 |
| Data deps. | 1.00 |
| Overall L1 | 6.75 |
| all | 22% |
| load | 25% |
| store | 25% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 33% |
| load | 25% |
| store | 25% |
| mul | 100% |
| add-sub | 50% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X26, X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X7, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X26, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4086e8 <.omp_outlined..5+0x168> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR Q5, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR Q6, [X7, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D16, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB V5.2D, V5.2D, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMUL V6.2D, V5.2D, V5.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FADDP D7, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D6, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB D6, D6, S16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D16, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D7, D6, D6, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FCMP D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| B.GT 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| FCMP D7, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| B.LE 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| FDIV D7, D0, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 7-15 | 1-0.50 |
| LDR D16, [X22] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D18, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X27, [X18, #48] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FMUL D17, D7, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FMUL D16, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FMUL D7, D7, D4 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FMUL D16, D17, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FNMSUB D17, D16, D16, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FMUL D7, D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FSUB D17, D17, S18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D18, [X27, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMUL D17, D17, D1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FADD D18, D17, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| STR D18, [X27, X4,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D18, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X27, [X18, #40] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| MADD X27, X4, X13, X27 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| FADD D17, D18, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMADD D18, D16, D2, D3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| LDR Q16, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| STR D17, [SP, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| LDR D17, [X9] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMUL D7, D7, D17 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FMUL D7, D7, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FMLA V16.2D, V5.2D, V7.D[0] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| LDR D5, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D5, D7, D6, D5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| STR Q16, [X27] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| STR D5, [X27, #16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0 | 0 | 0 | 2 | 0.50 |
| B 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | .omp_outlined..5#0x408580 |
| Source file and lines | ljForce.c:191-216 |
| Module | exec |
| nb instructions | 18 |
| loop length | 72 |
| nb stack references | 0 |
| front end | 2.25 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 1.75 | 1.75 | 1.50 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
| cycles | 1.50 | 1.50 | 0.75 | 0.75 | 0.75 | 0.75 | 2.00 | 1.75 | 1.75 | 1.50 | 1.67 | 1.67 | 1.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 2.25 |
| Data deps. | 1.00 |
| Overall L1 | 2.25 |
| all | 28% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 100% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 44% |
| load | 40% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 100% |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ADD X26, X26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X7, X7, #24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP X26, X2 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GE 4086e8 <.omp_outlined..5+0x168> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR Q5, [X5] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDUR Q6, [X7, #496] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D16, [X7] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB V5.2D, V5.2D, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| FMUL V6.2D, V5.2D, V5.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 3 | 0.25 |
| FADDP D7, V6.2D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D6, [X6] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FSUB D6, D6, S16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D16, [X23] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FMADD D7, D6, D6, D7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 4 | 0.25 |
| FCMP D7, D16 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| B.GT 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| FCMP D7, #0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 1 |
| B.LE 408708 <.omp_outlined..5+0x188> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
