| Loop Id: 13 | Module: exec | Source: initAtoms.c:177-181 | Coverage: 0.02% |
|---|
| Loop Id: 13 | Module: exec | Source: initAtoms.c:177-181 | Coverage: 0.02% |
|---|
0x4052e9 VMULPD (%RSI),%XMM1,%XMM2 [2] |
0x4052ed ADD $0xc0,%RSI |
0x4052f4 VMULSD -0xb0(%RSI),%XMM0,%XMM3 [1] |
0x4052fc VMULPD -0xa8(%RSI),%XMM1,%XMM4 [1] |
0x405304 VMULSD -0x98(%RSI),%XMM0,%XMM5 [1] |
0x40530c VMULPD -0x90(%RSI),%XMM1,%XMM6 [1] |
0x405314 VMOVUPD %XMM2,-0xc0(%RSI) [1] |
0x40531c VMULSD -0x80(%RSI),%XMM0,%XMM7 [1] |
0x405321 VMOVSD %XMM3,-0xb0(%RSI) [1] |
0x405329 VMULPD -0x78(%RSI),%XMM1,%XMM8 [1] |
0x40532e VMULSD -0x68(%RSI),%XMM0,%XMM9 [1] |
0x405333 VMOVUPD %XMM4,-0xa8(%RSI) [1] |
0x40533b VMULPD -0x60(%RSI),%XMM1,%XMM10 [1] |
0x405340 VMOVSD %XMM5,-0x98(%RSI) [1] |
0x405348 VMULSD -0x50(%RSI),%XMM0,%XMM11 [1] |
0x40534d VMOVUPD %XMM6,-0x90(%RSI) [1] |
0x405355 VMULPD -0x48(%RSI),%XMM1,%XMM12 [1] |
0x40535a VMOVSD %XMM7,-0x80(%RSI) [1] |
0x40535f VMULSD -0x38(%RSI),%XMM0,%XMM13 [1] |
0x405364 VMOVUPD %XMM8,-0x78(%RSI) [1] |
0x405369 VMULPD -0x30(%RSI),%XMM1,%XMM14 [1] |
0x40536e VMOVSD %XMM9,-0x68(%RSI) [1] |
0x405373 VMULSD -0x20(%RSI),%XMM0,%XMM15 [1] |
0x405378 VMOVUPD %XMM10,-0x60(%RSI) [1] |
0x40537d VMULPD -0x18(%RSI),%XMM1,%XMM2 [1] |
0x405382 VMOVSD %XMM11,-0x50(%RSI) [1] |
0x405387 VMULSD -0x8(%RSI),%XMM0,%XMM3 [1] |
0x40538c VMOVUPD %XMM12,-0x48(%RSI) [1] |
0x405391 VMOVSD %XMM13,-0x38(%RSI) [1] |
0x405396 VMOVUPD %XMM14,-0x30(%RSI) [1] |
0x40539b VMOVSD %XMM15,-0x20(%RSI) [1] |
0x4053a0 VMOVUPD %XMM2,-0x18(%RSI) [1] |
0x4053a5 VMOVSD %XMM3,-0x8(%RSI) [1] |
0x4053aa CMP %RDI,%RSI |
0x4053ad JNE 4052e9 |
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 177 - 181 |
-------------------------------------------------------------------------------- |
177: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
178: { |
179: s->atoms->p[iOff][0] *= scaleFactor; |
180: s->atoms->p[iOff][1] *= scaleFactor; |
181: s->atoms->p[iOff][2] *= scaleFactor; |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.33 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.41 |
| Bottlenecks | P0, P1, P4, P7, P8, P9, |
| Function | setTemperature._omp_fn.1 |
| Source | initAtoms.c:177-181 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 1.50 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 0.60 |
| P5 cycles | 1.00 |
| P6 cycles | 8.00 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 0.40 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.17 |
| Stall cycles (UFS) | 2.21 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 16.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 24.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 48.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 192.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 50.00 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | 50.00 |
| Vectorization ratio mul | 50.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 18.75 |
| Vector-efficiency ratio load | 18.75 |
| Vector-efficiency ratio store | 18.75 |
| Vector-efficiency ratio mul | 18.75 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.33 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.41 |
| Bottlenecks | P0, P1, P4, P7, P8, P9, |
| Function | setTemperature._omp_fn.1 |
| Source | initAtoms.c:177-181 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 8.00 |
| CQA cycles if no scalar integer | 8.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 1.50 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 8.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 8.00 |
| P4 cycles | 0.60 |
| P5 cycles | 1.00 |
| P6 cycles | 8.00 |
| P7 cycles | 8.00 |
| P8 cycles | 8.00 |
| P9 cycles | 0.40 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 8.17 |
| Stall cycles (UFS) | 2.21 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 16.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 3.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 24.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 48.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 192.00 |
| Bytes stored | 192.00 |
| Stride 0 | 0.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 1.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 50.00 |
| Vectorization ratio load | 50.00 |
| Vectorization ratio store | 50.00 |
| Vectorization ratio mul | 50.00 |
| Vectorization ratio add_sub | NA |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 18.75 |
| Vector-efficiency ratio load | 18.75 |
| Vector-efficiency ratio store | 18.75 |
| Vector-efficiency ratio mul | 18.75 |
| Vector-efficiency ratio add_sub | NA |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | setTemperature._omp_fn.1 |
| Source file and lines | initAtoms.c:177-181 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 202 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 8.00 | 5.33 | 5.33 | 8.00 | 0.60 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
| cycles | 8.00 | 8.00 | 5.33 | 5.33 | 8.00 | 0.60 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.17 |
| Stall cycles | 2.21 |
| RS full (events) | 7.59 |
| Front-end | 5.67 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 18% |
| load | 18% |
| store | 18% |
| mul | 18% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMULPD (%RSI),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0xc0,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMULSD -0xb0(%RSI),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD -0xa8(%RSI),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD -0x98(%RSI),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD -0x90(%RSI),%XMM1,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM2,-0xc0(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD -0x80(%RSI),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM3,-0xb0(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULPD -0x78(%RSI),%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD -0x68(%RSI),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM4,-0xa8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x60(%RSI),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM5,-0x98(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x50(%RSI),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM6,-0x90(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x48(%RSI),%XMM1,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM7,-0x80(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x38(%RSI),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM8,-0x78(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x30(%RSI),%XMM1,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM9,-0x68(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x20(%RSI),%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM10,-0x60(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x18(%RSI),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM11,-0x50(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x8(%RSI),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM12,-0x48(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM13,-0x38(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPD %XMM14,-0x30(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM15,-0x20(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPD %XMM2,-0x18(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM3,-0x8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 4052e9 <setTemperature._omp_fn.1+0x199> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | setTemperature._omp_fn.1 |
| Source file and lines | initAtoms.c:177-181 |
| Module | exec |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 202 |
| used x86 registers | 2 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 8.00 | 5.33 | 5.33 | 8.00 | 0.60 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
| cycles | 8.00 | 8.00 | 5.33 | 5.33 | 8.00 | 0.60 | 1.00 | 8.00 | 8.00 | 8.00 | 0.40 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 8.17 |
| Stall cycles | 2.21 |
| RS full (events) | 7.59 |
| Front-end | 5.67 |
| Dispatch | 8.00 |
| Data deps. | 1.00 |
| Overall L1 | 8.00 |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | 50% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 18% |
| load | 18% |
| store | 18% |
| mul | 18% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMULPD (%RSI),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0xc0,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMULSD -0xb0(%RSI),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD -0xa8(%RSI),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD -0x98(%RSI),%XMM0,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULPD -0x90(%RSI),%XMM1,%XMM6 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM2,-0xc0(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULSD -0x80(%RSI),%XMM0,%XMM7 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM3,-0xb0(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULPD -0x78(%RSI),%XMM1,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD -0x68(%RSI),%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM4,-0xa8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x60(%RSI),%XMM1,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM5,-0x98(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x50(%RSI),%XMM0,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM6,-0x90(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x48(%RSI),%XMM1,%XMM12 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM7,-0x80(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x38(%RSI),%XMM0,%XMM13 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM8,-0x78(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x30(%RSI),%XMM1,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM9,-0x68(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x20(%RSI),%XMM0,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM10,-0x60(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMULPD -0x18(%RSI),%XMM1,%XMM2 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD %XMM11,-0x50(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMULSD -0x8(%RSI),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVUPD %XMM12,-0x48(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM13,-0x38(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPD %XMM14,-0x30(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM15,-0x20(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPD %XMM2,-0x18(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD %XMM3,-0x8(%RSI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CMP %RDI,%RSI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 4052e9 <setTemperature._omp_fn.1+0x199> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
