| Function: randomDisplacements._omp_fn.0 | Module: exec | Source: initAtoms.c:194-202 [...] | Coverage: 0.03% |
|---|
| Function: randomDisplacements._omp_fn.0 | Module: exec | Source: initAtoms.c:194-202 [...] | Coverage: 0.03% |
|---|
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 45 - 70 |
-------------------------------------------------------------------------------- |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
[...] |
68: uint32_t s2 = (id+callSite) * UINT32_C(2654435761); |
69: |
70: uint64_t iSeed = (UINT64_C(0x100000000) * s1) + s2; |
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 194 - 202 |
-------------------------------------------------------------------------------- |
194: #pragma omp parallel for |
195: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
196: { |
197: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
198: { |
199: uint64_t seed = mkSeed(s->atoms->gid[iOff], 457); |
200: s->atoms->r[iOff][0] += (2.0*lcg61(&seed)-1.0) * delta; |
201: s->atoms->r[iOff][1] += (2.0*lcg61(&seed)-1.0) * delta; |
202: s->atoms->r[iOff][2] += (2.0*lcg61(&seed)-1.0) * delta; |
0x4053e0 PUSH %RBP |
0x4053e1 MOV %RSP,%RBP |
0x4053e4 PUSH %R15 |
0x4053e6 PUSH %R14 |
0x4053e8 PUSH %R13 |
0x4053ea MOV %RDI,%R13 |
0x4053ed PUSH %R12 |
0x4053ef PUSH %RBX |
0x4053f0 SUB $0x8,%RSP |
0x4053f4 MOV (%RDI),%RBX |
0x4053f7 CALL 403060 <omp_get_num_threads@plt> |
0x4053fc MOV 0x18(%RBX),%R15 |
0x405400 MOV %EAX,%R12D |
0x405403 CALL 403150 <omp_get_thread_num@plt> |
0x405408 MOV %EAX,%R11D |
0x40540b MOV 0xc(%R15),%EAX |
0x40540f CLTD |
0x405410 IDIV %R12D |
0x405413 CMP %EDX,%R11D |
0x405416 JL 405745 |
0x40541c IMUL %EAX,%R11D |
0x405420 ADD %EDX,%R11D |
0x405423 LEA (%RAX,%R11,1),%R14D |
0x405427 CMP %R14D,%R11D |
0x40542a JGE 405736 |
0x405430 VMOVSD 0x8(%R13),%XMM1 |
0x405436 MOV 0x78(%R15),%R12 |
0x40543a MOVSXD %R11D,%R13 |
0x40543d VXORPS %XMM7,%XMM7,%XMM7 |
0x405441 VMOVDDUP 0xc79f(%RIP),%XMM5 |
0x405449 VMOVDDUP 0xc877(%RIP),%XMM4 |
0x405451 VMOVSD 0xc78f(%RIP),%XMM3 |
0x405459 VMOVSD 0xc867(%RIP),%XMM2 |
0x405461 SAL $0x6,%R11D |
0x405465 MOV $0x613606df9756715,%RDI |
0x40546f VMOVDDUP %XMM1,%XMM6 |
0x405473 MOV $0x9,%ESI |
0x405478 NOPL (%RAX,%RAX,1) |
(14) 0x405480 MOVSXD (%R12,%R13,4),%R15 |
(14) 0x405484 TEST %R15D,%R15D |
(14) 0x405487 JLE 405726 |
(14) 0x40548d MOV 0x20(%RBX),%R8 |
(14) 0x405491 MOVSXD %R11D,%RCX |
(14) 0x405494 LEA (%RCX,%RCX,2),%R10 |
(14) 0x405498 MOV 0x8(%R8),%RAX |
(14) 0x40549c MOV 0x18(%R8),%RDX |
(14) 0x4054a0 LEA (%RAX,%RCX,4),%R9 |
(14) 0x4054a4 MOV %R13,%RCX |
(14) 0x4054a7 LEA (%RDX,%R10,8),%R8 |
(14) 0x4054ab SAL $0x6,%RCX |
(14) 0x4054af ADD %RCX,%R15 |
(14) 0x4054b2 LEA (%RAX,%R15,4),%R10 |
(14) 0x4054b6 NOPW %CS:(%RAX,%RAX,1) |
(15) 0x4054c0 MOV (%R9),%R15D |
(15) 0x4054c3 IMUL $-0x61c8864f,%R15D,%ECX |
(15) 0x4054ca ADD $0x1c9,%R15D |
(15) 0x4054d1 IMUL $-0x61c8864f,%R15D,%EAX |
(15) 0x4054d8 SAL $0x20,%RCX |
(15) 0x4054dc ADD %RAX,%RCX |
(15) 0x4054df IMUL %RDI,%RCX |
(15) 0x4054e3 MOV %RCX,%RAX |
(15) 0x4054e6 MOV %RCX,%R15 |
(15) 0x4054e9 MUL %RSI |
(15) 0x4054ec SUB %RDX,%R15 |
(15) 0x4054ef SHR $0x1,%R15 |
(15) 0x4054f2 ADD %R15,%RDX |
(15) 0x4054f5 SHR $0x3c,%RDX |
(15) 0x4054f9 MOV %RDX,%RAX |
(15) 0x4054fc SAL $0x3d,%RAX |
(15) 0x405500 SUB %RDX,%RAX |
(15) 0x405503 SUB %RAX,%RCX |
(15) 0x405506 IMUL %RDI,%RCX |
(15) 0x40550a MOV %RCX,%RAX |
(15) 0x40550d MOV %RCX,%R15 |
(15) 0x405510 MUL %RSI |
(15) 0x405513 SUB %RDX,%R15 |
(15) 0x405516 SHR $0x1,%R15 |
(15) 0x405519 ADD %R15,%RDX |
(15) 0x40551c SHR $0x3c,%RDX |
(15) 0x405520 MOV %RDX,%RAX |
(15) 0x405523 SAL $0x3d,%RAX |
(15) 0x405527 SUB %RDX,%RAX |
(15) 0x40552a SUB %RAX,%RCX |
(15) 0x40552d IMUL %RDI,%RCX |
(15) 0x405531 MOV %RCX,%RAX |
(15) 0x405534 MOV %RCX,%R15 |
(15) 0x405537 MUL %RSI |
(15) 0x40553a SUB %RDX,%R15 |
(15) 0x40553d SHR $0x1,%R15 |
(15) 0x405540 ADD %R15,%RDX |
(15) 0x405543 SHR $0x3c,%RDX |
(15) 0x405547 MOV %RDX,%RAX |
(15) 0x40554a SAL $0x3d,%RAX |
(15) 0x40554e SUB %RDX,%RAX |
(15) 0x405551 SUB %RAX,%RCX |
(15) 0x405554 IMUL %RDI,%RCX |
(15) 0x405558 MOV %RCX,%RAX |
(15) 0x40555b MOV %RCX,%R15 |
(15) 0x40555e MUL %RSI |
(15) 0x405561 SUB %RDX,%R15 |
(15) 0x405564 SHR $0x1,%R15 |
(15) 0x405567 ADD %R15,%RDX |
(15) 0x40556a SHR $0x3c,%RDX |
(15) 0x40556e MOV %RDX,%RAX |
(15) 0x405571 SAL $0x3d,%RAX |
(15) 0x405575 SUB %RDX,%RAX |
(15) 0x405578 SUB %RAX,%RCX |
(15) 0x40557b IMUL %RDI,%RCX |
(15) 0x40557f MOV %RCX,%RAX |
(15) 0x405582 MOV %RCX,%R15 |
(15) 0x405585 MUL %RSI |
(15) 0x405588 SUB %RDX,%R15 |
(15) 0x40558b SHR $0x1,%R15 |
(15) 0x40558e ADD %R15,%RDX |
(15) 0x405591 SHR $0x3c,%RDX |
(15) 0x405595 MOV %RDX,%RAX |
(15) 0x405598 SAL $0x3d,%RAX |
(15) 0x40559c SUB %RDX,%RAX |
(15) 0x40559f SUB %RAX,%RCX |
(15) 0x4055a2 IMUL %RDI,%RCX |
(15) 0x4055a6 MOV %RCX,%RAX |
(15) 0x4055a9 MOV %RCX,%R15 |
(15) 0x4055ac MUL %RSI |
(15) 0x4055af SUB %RDX,%R15 |
(15) 0x4055b2 SHR $0x1,%R15 |
(15) 0x4055b5 ADD %R15,%RDX |
(15) 0x4055b8 SHR $0x3c,%RDX |
(15) 0x4055bc MOV %RDX,%RAX |
(15) 0x4055bf SAL $0x3d,%RAX |
(15) 0x4055c3 SUB %RDX,%RAX |
(15) 0x4055c6 SUB %RAX,%RCX |
(15) 0x4055c9 IMUL %RDI,%RCX |
(15) 0x4055cd MOV %RCX,%RAX |
(15) 0x4055d0 MOV %RCX,%R15 |
(15) 0x4055d3 MUL %RSI |
(15) 0x4055d6 SUB %RDX,%R15 |
(15) 0x4055d9 SHR $0x1,%R15 |
(15) 0x4055dc ADD %R15,%RDX |
(15) 0x4055df SHR $0x3c,%RDX |
(15) 0x4055e3 MOV %RDX,%RAX |
(15) 0x4055e6 SAL $0x3d,%RAX |
(15) 0x4055ea SUB %RDX,%RAX |
(15) 0x4055ed SUB %RAX,%RCX |
(15) 0x4055f0 IMUL %RDI,%RCX |
(15) 0x4055f4 MOV %RCX,%RAX |
(15) 0x4055f7 MOV %RCX,%R15 |
(15) 0x4055fa MUL %RSI |
(15) 0x4055fd SUB %RDX,%R15 |
(15) 0x405600 SHR $0x1,%R15 |
(15) 0x405603 ADD %R15,%RDX |
(15) 0x405606 SHR $0x3c,%RDX |
(15) 0x40560a MOV %RDX,%RAX |
(15) 0x40560d SAL $0x3d,%RAX |
(15) 0x405611 SUB %RDX,%RAX |
(15) 0x405614 SUB %RAX,%RCX |
(15) 0x405617 IMUL %RDI,%RCX |
(15) 0x40561b MOV %RCX,%RAX |
(15) 0x40561e MOV %RCX,%R15 |
(15) 0x405621 MUL %RSI |
(15) 0x405624 SUB %RDX,%R15 |
(15) 0x405627 SHR $0x1,%R15 |
(15) 0x40562a ADD %R15,%RDX |
(15) 0x40562d SHR $0x3c,%RDX |
(15) 0x405631 MOV %RDX,%RAX |
(15) 0x405634 SAL $0x3d,%RAX |
(15) 0x405638 SUB %RDX,%RAX |
(15) 0x40563b SUB %RAX,%RCX |
(15) 0x40563e IMUL %RDI,%RCX |
(15) 0x405642 MOV %RCX,%RAX |
(15) 0x405645 MOV %RCX,%R15 |
(15) 0x405648 MUL %RSI |
(15) 0x40564b SUB %RDX,%R15 |
(15) 0x40564e SHR $0x1,%R15 |
(15) 0x405651 ADD %R15,%RDX |
(15) 0x405654 SHR $0x3c,%RDX |
(15) 0x405658 MOV %RDX,%RAX |
(15) 0x40565b SAL $0x3d,%RAX |
(15) 0x40565f SUB %RDX,%RAX |
(15) 0x405662 SUB %RAX,%RCX |
(15) 0x405665 IMUL %RDI,%RCX |
(15) 0x405669 MOV %RCX,%RAX |
(15) 0x40566c MOV %RCX,%R15 |
(15) 0x40566f MUL %RSI |
(15) 0x405672 ADD $0x4,%R9 |
(15) 0x405676 ADD $0x18,%R8 |
(15) 0x40567a SUB %RDX,%R15 |
(15) 0x40567d SHR $0x1,%R15 |
(15) 0x405680 ADD %RDX,%R15 |
(15) 0x405683 SHR $0x3c,%R15 |
(15) 0x405687 MOV %R15,%RAX |
(15) 0x40568a SAL $0x3d,%RAX |
(15) 0x40568e SUB %R15,%RAX |
(15) 0x405691 SUB %RAX,%RCX |
(15) 0x405694 MOV %RCX,%R15 |
(15) 0x405697 VMOVQ %RCX,%XMM0 |
(15) 0x40569c IMUL %RDI,%R15 |
(15) 0x4056a0 MOV %R15,%RAX |
(15) 0x4056a3 MUL %RSI |
(15) 0x4056a6 MOV %R15,%RAX |
(15) 0x4056a9 SUB %RDX,%RAX |
(15) 0x4056ac SHR $0x1,%RAX |
(15) 0x4056af ADD %RAX,%RDX |
(15) 0x4056b2 SHR $0x3c,%RDX |
(15) 0x4056b6 MOV %RDX,%RAX |
(15) 0x4056b9 SAL $0x3d,%RAX |
(15) 0x4056bd SUB %RDX,%RAX |
(15) 0x4056c0 SUB %RAX,%R15 |
(15) 0x4056c3 VPINSRQ $0x1,%R15,%XMM0,%XMM8 |
(15) 0x4056c9 IMUL %RDI,%R15 |
(15) 0x4056cd VCVTQQ2PD %XMM8,%XMM9 |
(15) 0x4056d3 VFMADD132PD %XMM5,%XMM4,%XMM9 |
(15) 0x4056d8 MOV %R15,%RAX |
(15) 0x4056db MOV %R15,%RCX |
(15) 0x4056de MUL %RSI |
(15) 0x4056e1 VFMADD213PD -0x18(%R8),%XMM6,%XMM9 |
(15) 0x4056e7 SUB %RDX,%RCX |
(15) 0x4056ea SHR $0x1,%RCX |
(15) 0x4056ed ADD %RCX,%RDX |
(15) 0x4056f0 SHR $0x3c,%RDX |
(15) 0x4056f4 MOV %RDX,%RAX |
(15) 0x4056f7 VMOVUPD %XMM9,-0x18(%R8) |
(15) 0x4056fd SAL $0x3d,%RAX |
(15) 0x405701 SUB %RDX,%RAX |
(15) 0x405704 SUB %RAX,%R15 |
(15) 0x405707 VCVTSI2SD %R15,%XMM7,%XMM10 |
(15) 0x40570c VFMADD132SD %XMM3,%XMM2,%XMM10 |
(15) 0x405711 VFMADD213SD -0x8(%R8),%XMM1,%XMM10 |
(15) 0x405717 VMOVSD %XMM10,-0x8(%R8) |
(15) 0x40571d CMP %R9,%R10 |
(15) 0x405720 JNE 4054c0 |
(14) 0x405726 INC %R13 |
(14) 0x405729 ADD $0x40,%R11D |
(14) 0x40572d CMP %R13D,%R14D |
(14) 0x405730 JG 405480 |
0x405736 ADD $0x8,%RSP |
0x40573a POP %RBX |
0x40573b POP %R12 |
0x40573d POP %R13 |
0x40573f POP %R14 |
0x405741 POP %R15 |
0x405743 POP %RBP |
0x405744 RET |
0x405745 INC %EAX |
0x405747 XOR %EDX,%EDX |
0x405749 JMP 40541c |
0x40574e XCHG %AX,%AX |
| Path / |
| Source file and lines | initAtoms.c:194-202 |
| Module | exec |
| nb instructions | 50 |
| nb uops | 55 |
| loop length | 186 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 4.00 | 5.33 | 5.33 | 4.00 | 3.60 | 3.50 | 4.00 | 4.00 | 4.00 | 3.40 | 5.33 |
| cycles | 3.50 | 5.73 | 5.33 | 5.33 | 4.00 | 3.60 | 3.50 | 4.00 | 4.00 | 4.00 | 3.40 | 5.33 |
| Cycles executing div or sqrt instructions | 6.00 |
| FE+BE cycles | 8.87-8.90 |
| Stall cycles | 0.00 |
| Front-end | 9.17 |
| Dispatch | 5.73 |
| DIV/SQRT | 6.00 |
| Overall L1 | 9.17 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 5% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 11% |
| all | 8% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 7% |
| all | 14% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 10% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 9% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV 0xc(%R15),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
| CMP %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JL 405745 <randomDisplacements._omp_fn.0+0x365> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| LEA (%RAX,%R11,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| CMP %R14D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 405736 <randomDisplacements._omp_fn.0+0x356> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVSD 0x8(%R13),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x78(%R15),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOVSXD %R11D,%R13 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
| VXORPS %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVDDUP 0xc79f(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVDDUP 0xc877(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0xc78f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0xc867(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| SAL $0x6,%R11D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
| MOV $0x613606df9756715,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| VMOVDDUP %XMM1,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| JMP 40541c <randomDisplacements._omp_fn.0+0x3c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Source file and lines | initAtoms.c:194-202 |
| Module | exec |
| nb instructions | 50 |
| nb uops | 55 |
| loop length | 186 |
| used x86 registers | 12 |
| used mmx registers | 0 |
| used xmm registers | 7 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 9.17 cycles |
| front end | 9.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 3.50 | 4.00 | 5.33 | 5.33 | 4.00 | 3.60 | 3.50 | 4.00 | 4.00 | 4.00 | 3.40 | 5.33 |
| cycles | 3.50 | 5.73 | 5.33 | 5.33 | 4.00 | 3.60 | 3.50 | 4.00 | 4.00 | 4.00 | 3.40 | 5.33 |
| Cycles executing div or sqrt instructions | 6.00 |
| FE+BE cycles | 8.87-8.90 |
| Stall cycles | 0.00 |
| Front-end | 9.17 |
| Dispatch | 5.73 |
| DIV/SQRT | 6.00 |
| Overall L1 | 9.17 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 50% |
| all | 5% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 11% |
| all | 8% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 7% |
| all | 14% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 18% |
| all | 10% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 6% |
| other | 9% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RDI,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV (%RDI),%RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CALL 403060 <omp_get_num_threads@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| MOV 0x18(%RBX),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %EAX,%R12D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CALL 403150 <omp_get_thread_num@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| MOV %EAX,%R11D | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV 0xc(%R15),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CLTD | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| IDIV %R12D | 4 | 0 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 11-16 | 6 |
| CMP %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JL 405745 <randomDisplacements._omp_fn.0+0x365> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| IMUL %EAX,%R11D | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| ADD %EDX,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| LEA (%RAX,%R11,1),%R14D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1-2 | 0.20 |
| CMP %R14D,%R11D | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JGE 405736 <randomDisplacements._omp_fn.0+0x356> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| VMOVSD 0x8(%R13),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x78(%R15),%R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOVSXD %R11D,%R13 | 1 | 0 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0.33 | 0 | 1 | 0.33 |
| VXORPS %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VMOVDDUP 0xc79f(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVDDUP 0xc877(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0xc78f(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0xc867(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| SAL $0x6,%R11D | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
| MOV $0x613606df9756715,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| VMOVDDUP %XMM1,%XMM6 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| ADD $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| INC %EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| XOR %EDX,%EDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| JMP 40541c <randomDisplacements._omp_fn.0+0x3c> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼randomDisplacements._omp_fn.0– | 0.03 | 0 |
| ▼Loop 14 - initAtoms.c:197-202 - exec– | 0 | 0 |
| ○Loop 15 - initAtoms.c:197-202 - exec | 0.03 | 0 |
