| Loop Id: 64 | Module: exec | Source: initAtoms.c:126-133 | Coverage: 0.01% |
|---|
| Loop Id: 64 | Module: exec | Source: initAtoms.c:126-133 | Coverage: 0.01% |
|---|
0x40a8c0 VPBROADCASTQ %RDX,%YMM7 |
0x40a8c6 VPADDQ %YMM7,%YMM4,%YMM7 |
0x40a8ca VPSLLQ $0x3,%YMM7,%YMM8 |
0x40a8cf VPSLLQ $0x4,%YMM7,%YMM7 |
0x40a8d4 VPADDQ %YMM7,%YMM8,%YMM7 |
0x40a8d8 KXNORW %K0,%K0,%K1 |
0x40a8dc VPXOR %XMM8,%XMM8,%XMM8 |
0x40a8e1 VGATHERQPD (%R11,%YMM7,1),%YMM8{%K1} [2] |
0x40a8e8 VPMOVSXDQ (%R13,%RDX,4),%YMM9 [1] |
0x40a8ef VPSLLQ $0x4,%YMM9,%YMM9 |
0x40a8f5 KXNORW %K0,%K0,%K1 |
0x40a8f9 VXORPD %XMM10,%XMM10,%XMM10 |
0x40a8fe VGATHERQPD 0x8(%R9,%YMM9,1),%YMM10{%K1} [3] |
0x40a906 VFMADD231PD %YMM10,%YMM3,%YMM8 |
0x40a90b KXNORW %K0,%K0,%K1 |
0x40a90f VSCATTERQPD %YMM8,(%R11,%YMM7,1){%K1} [2] |
0x40a916 KXNORW %K0,%K0,%K1 |
0x40a91a VXORPD %XMM8,%XMM8,%XMM8 |
0x40a91f VGATHERQPD 0x8(%R11,%YMM7,1),%YMM8{%K1} [2] |
0x40a927 VFMADD231PD %YMM10,%YMM5,%YMM8 |
0x40a92c KXNORW %K0,%K0,%K1 |
0x40a930 VSCATTERQPD %YMM8,0x8(%R11,%YMM7,1){%K1} [2] |
0x40a938 KXNORW %K0,%K0,%K1 |
0x40a93c VXORPD %XMM8,%XMM8,%XMM8 |
0x40a941 VGATHERQPD 0x10(%R11,%YMM7,1),%YMM8{%K1} [2] |
0x40a949 VFMADD231PD %YMM10,%YMM6,%YMM8 |
0x40a94e KXNORW %K0,%K0,%K1 |
0x40a952 VSCATTERQPD %YMM8,0x10(%R11,%YMM7,1){%K1} [2] |
0x40a95a ADD $0x4,%RDX |
0x40a95e CMP %R15D,%EDX |
0x40a961 JLE 40a8c0 |
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 126 - 133 |
-------------------------------------------------------------------------------- |
126: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
127: { |
128: int iSpecies = s->atoms->iSpecies[iOff]; |
129: real_t mass = s->species[iSpecies].mass; |
130: |
131: s->atoms->p[iOff][0] += mass * vShift[0]; |
132: s->atoms->p[iOff][1] += mass * vShift[1]; |
133: s->atoms->p[iOff][2] += mass * vShift[2]; |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.17 |
| CQA speedup if FP arith vectorized | 1.33 |
| CQA speedup if fully vectorized | 2.92 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P0, |
| Function | setVcm.extracted |
| Source | initAtoms.c:126-133 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 14.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 10.50 |
| CQA cycles if fully vectorized | 4.79 |
| Front-end cycles | 13.33 |
| DIV/SQRT cycles | 14.00 |
| P0 cycles | 10.50 |
| P1 cycles | 5.67 |
| P2 cycles | 5.67 |
| P3 cycles | 6.00 |
| P4 cycles | 10.50 |
| P5 cycles | 2.00 |
| P6 cycles | 6.00 |
| P7 cycles | 6.00 |
| P8 cycles | 6.00 |
| P9 cycles | 2.00 |
| P10 cycles | 5.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 14.29 - 89.45 |
| Stall cycles (UFS) | 3.77 - 78.76 |
| Nb insns | 31.00 |
| Nb uops | 80.00 |
| Nb loads | 5.00 |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.71 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.14 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 144.00 |
| Bytes stored | 96.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 95.24 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 91.67 |
| Vector-efficiency ratio all | 42.26 |
| Vector-efficiency ratio load | 45.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 38.54 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.17 |
| CQA speedup if FP arith vectorized | 1.33 |
| CQA speedup if fully vectorized | 2.92 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.05 |
| Bottlenecks | P0, |
| Function | setVcm.extracted |
| Source | initAtoms.c:126-133 |
| Source loop unroll info | unrolled by 4 |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | main |
| Unroll factor | 4 |
| CQA cycles | 14.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 10.50 |
| CQA cycles if fully vectorized | 4.79 |
| Front-end cycles | 13.33 |
| DIV/SQRT cycles | 14.00 |
| P0 cycles | 10.50 |
| P1 cycles | 5.67 |
| P2 cycles | 5.67 |
| P3 cycles | 6.00 |
| P4 cycles | 10.50 |
| P5 cycles | 2.00 |
| P6 cycles | 6.00 |
| P7 cycles | 6.00 |
| P8 cycles | 6.00 |
| P9 cycles | 2.00 |
| P10 cycles | 5.67 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 14.29 - 89.45 |
| Stall cycles (UFS) | 3.77 - 78.76 |
| Nb insns | 31.00 |
| Nb uops | 80.00 |
| Nb loads | 5.00 |
| Nb stores | 3.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.71 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 12.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.14 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 144.00 |
| Bytes stored | 96.00 |
| Stride 0 | 0.00 |
| Stride 1 | 1.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 2.00 |
| Vectorization ratio all | 95.24 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | 100.00 |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 91.67 |
| Vector-efficiency ratio all | 42.26 |
| Vector-efficiency ratio load | 45.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | 50.00 |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 38.54 |
| Path / |
| Function | setVcm.extracted |
| Source file and lines | initAtoms.c:126-133 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 80 |
| loop length | 167 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 8 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 13.33 cycles |
| front end | 13.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.00 | 10.50 | 5.67 | 5.67 | 6.00 | 10.50 | 2.00 | 6.00 | 6.00 | 6.00 | 2.00 | 5.67 |
| cycles | 14.00 | 10.50 | 5.67 | 5.67 | 6.00 | 10.50 | 2.00 | 6.00 | 6.00 | 6.00 | 2.00 | 5.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 14.29-89.45 |
| Stall cycles | 3.77-78.76 |
| RS full (events) | 9.64-87.44 |
| Front-end | 13.33 |
| Dispatch | 14.00 |
| Data deps. | 1.00 |
| Overall L1 | 14.00 |
| all | 87% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 80% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 91% |
| all | 39% |
| load | 25% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 37% |
| all | 44% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 39% |
| all | 42% |
| load | 45% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 38% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPBROADCASTQ %RDX,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDQ %YMM7,%YMM4,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPSLLQ $0x3,%YMM7,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPSLLQ $0x4,%YMM7,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPADDQ %YMM7,%YMM8,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXOR %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VPMOVSXDQ (%R13,%RDX,4),%YMM9 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
| VPSLLQ $0x4,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x8(%R9,%YMM9,1),%YMM10{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM3,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x8(%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM5,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,0x8(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x10(%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,0x10(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| ADD $0x4,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JLE 40a8c0 <setVcm.extracted+0x170> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | setVcm.extracted |
| Source file and lines | initAtoms.c:126-133 |
| Module | exec |
| nb instructions | 31 |
| nb uops | 80 |
| loop length | 167 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 2 |
| used ymm registers | 8 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 13.33 cycles |
| front end | 13.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 14.00 | 10.50 | 5.67 | 5.67 | 6.00 | 10.50 | 2.00 | 6.00 | 6.00 | 6.00 | 2.00 | 5.67 |
| cycles | 14.00 | 10.50 | 5.67 | 5.67 | 6.00 | 10.50 | 2.00 | 6.00 | 6.00 | 6.00 | 2.00 | 5.67 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 14.29-89.45 |
| Stall cycles | 3.77-78.76 |
| RS full (events) | 9.64-87.44 |
| Front-end | 13.33 |
| Dispatch | 14.00 |
| Data deps. | 1.00 |
| Overall L1 | 14.00 |
| all | 87% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 80% |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 95% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | 100% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 91% |
| all | 39% |
| load | 25% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 37% |
| all | 44% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 39% |
| all | 42% |
| load | 45% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | 50% |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 38% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VPBROADCASTQ %RDX,%YMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 1 |
| VPADDQ %YMM7,%YMM4,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VPSLLQ $0x3,%YMM7,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPSLLQ $0x4,%YMM7,%YMM7 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| VPADDQ %YMM7,%YMM8,%YMM7 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VPXOR %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD (%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VPMOVSXDQ (%R13,%RDX,4),%YMM9 | 2 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 1 |
| VPSLLQ $0x4,%YMM9,%YMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2-4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM10,%XMM10,%XMM10 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x8(%R9,%YMM9,1),%YMM10{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM3,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x8(%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM5,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,0x8(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VXORPD %XMM8,%XMM8,%XMM8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VGATHERQPD 0x10(%R11,%YMM7,1),%YMM8{%K1} | 5 | 1 | 1 | 1.33 | 1.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1.33 | 0-29 | 2 |
| VFMADD231PD %YMM10,%YMM6,%YMM8 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| KXNORW %K0,%K0,%K1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| VSCATTERQPD %YMM8,0x10(%R11,%YMM7,1){%K1} | 12 | 1.70 | 0.70 | 0 | 0 | 2 | 0.20 | 0.20 | 2 | 2 | 2 | 0.20 | 0 | 2-12 | 5 |
| ADD $0x4,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R15D,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JLE 40a8c0 <setVcm.extracted+0x170> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
