| Function: gasdev | Module: exec | Source: random.c:22-48 [...] | Coverage: 0.01% |
|---|
| Function: gasdev | Module: exec | Source: random.c:22-48 [...] | Coverage: 0.01% |
|---|
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 22 - 48 |
-------------------------------------------------------------------------------- |
22: { |
23: real_t rsq,v1,v2; |
24: do |
25: { |
26: v1 = 2.0*lcg61(seed)-1.0; |
27: v2 = 2.0*lcg61(seed)-1.0; |
28: rsq = v1*v1+v2*v2; |
29: } while (rsq >= 1.0 || rsq == 0.0); |
30: |
31: return v2 * sqrt(-2.0*log(rsq)/rsq); |
[...] |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
0x40e830 MOV $0x613606df9756715,%RCX |
0x40e83a MOV (%RDI),%RDX |
0x40e83d MOV $0x9,%ESI |
0x40e842 VMOVSD 0x14a76(%RIP),%XMM5 |
0x40e84a VMOVSD 0x15f5e(%RIP),%XMM1 |
0x40e852 VMOVSD 0x1392e(%RIP),%XMM2 |
0x40e85a VXORPD %XMM3,%XMM3,%XMM3 |
0x40e85e XCHG %AX,%AX |
(91) 0x40e860 IMUL %RCX,%RDX |
(91) 0x40e864 MULX %RSI,%R8,%R8 |
(91) 0x40e869 MOV %RDX,%RAX |
(91) 0x40e86c SUB %R8,%RAX |
(91) 0x40e86f SHR $0x1,%RAX |
(91) 0x40e872 ADD %R8,%RAX |
(91) 0x40e875 SHR $0x3c,%RAX |
(91) 0x40e879 MOV %RAX,%R8 |
(91) 0x40e87c SAL $0x3d,%R8 |
(91) 0x40e880 SUB %R8,%RAX |
(91) 0x40e883 ADD %RDX,%RAX |
(91) 0x40e886 VCVTSI2SD %RAX,%XMM7,%XMM0 |
(91) 0x40e88b IMUL %RCX,%RAX |
(91) 0x40e88f MOV %RAX,%RDX |
(91) 0x40e892 MULX %RSI,%R8,%R8 |
(91) 0x40e897 SUB %R8,%RDX |
(91) 0x40e89a SHR $0x1,%RDX |
(91) 0x40e89d ADD %R8,%RDX |
(91) 0x40e8a0 SHR $0x3c,%RDX |
(91) 0x40e8a4 MOV %RDX,%R8 |
(91) 0x40e8a7 SAL $0x3d,%R8 |
(91) 0x40e8ab SUB %R8,%RDX |
(91) 0x40e8ae ADD %RAX,%RDX |
(91) 0x40e8b1 VCVTSI2SD %RDX,%XMM7,%XMM6 |
(91) 0x40e8b6 VFMADD213SD %XMM5,%XMM1,%XMM6 |
(91) 0x40e8bb VMULSD %XMM6,%XMM6,%XMM4 |
(91) 0x40e8bf VFMADD213SD %XMM5,%XMM1,%XMM0 |
(91) 0x40e8c4 VFMADD213SD %XMM4,%XMM0,%XMM0 |
(91) 0x40e8c9 VUCOMISD %XMM2,%XMM0 |
(91) 0x40e8cd JAE 40e860 |
(91) 0x40e8cf VUCOMISD %XMM3,%XMM0 |
(91) 0x40e8d3 JE 40e860 |
0x40e8d5 PUSH %RBP |
0x40e8d6 MOV %RSP,%RBP |
0x40e8d9 SUB $0x10,%RSP |
0x40e8dd MOV %RDX,(%RDI) |
0x40e8e0 VMOVSD %XMM0,-0x8(%RBP) |
0x40e8e5 VMOVSD %XMM6,-0x10(%RBP) |
0x40e8ea CALL 40fdd0 <log> |
0x40e8ef VMULSD 0x15ec1(%RIP),%XMM0,%XMM0 |
0x40e8f7 VDIVSD -0x8(%RBP),%XMM0,%XMM0 |
0x40e8fc VSQRTSD %XMM0,%XMM0,%XMM0 |
0x40e900 VMULSD -0x10(%RBP),%XMM0,%XMM0 |
0x40e905 ADD $0x10,%RSP |
0x40e909 POP %RBP |
0x40e90a RET |
0x40e90b NOPL (%RAX,%RAX,1) |
| Path / |
| Source file and lines | random.c:22-48 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 24 |
| loop length | 107 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 3.00 | 3.00 | 2.50 | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 1.00 | 3.00 |
| cycles | 2.00 | 2.00 | 3.00 | 3.00 | 2.50 | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 1.00 | 3.00 |
| Cycles executing div or sqrt instructions | 8.50 |
| FE+BE cycles | 34.12-42.12 |
| Stall cycles | 29.44-37.44 |
| ROB full (events) | 31.23-39.24 |
| Front-end | 4.00 |
| Dispatch | 3.00 |
| DIV/SQRT | 8.50 |
| Overall L1 | 8.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 100% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 25% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV $0x613606df9756715,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| MOV (%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMOVSD 0x14a76(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x15f5e(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x1392e(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SUB $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RDX,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM0,-0x8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM6,-0x10(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 40fdd0 <log> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| VMULSD 0x15ec1(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VDIVSD -0x8(%RBP),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VSQRTSD %XMM0,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VMULSD -0x10(%RBP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Source file and lines | random.c:22-48 |
| Module | exec |
| nb instructions | 23 |
| nb uops | 24 |
| loop length | 107 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 6 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 4.00 cycles |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.00 | 2.00 | 3.00 | 3.00 | 2.50 | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 1.00 | 3.00 |
| cycles | 2.00 | 2.00 | 3.00 | 3.00 | 2.50 | 1.00 | 1.00 | 2.50 | 2.50 | 2.50 | 1.00 | 3.00 |
| Cycles executing div or sqrt instructions | 8.50 |
| FE+BE cycles | 34.12-42.12 |
| Stall cycles | 29.44-37.44 |
| ROB full (events) | 31.23-39.24 |
| Front-end | 4.00 |
| Dispatch | 3.00 |
| DIV/SQRT | 8.50 |
| Overall L1 | 8.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 10% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 100% |
| all | 7% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 33% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 9% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 25% |
| all | 12% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 14% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV $0x613606df9756715,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| MOV (%RDI),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VMOVSD 0x14a76(%RIP),%XMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x15f5e(%RIP),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x1392e(%RIP),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VXORPD %XMM3,%XMM3,%XMM3 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| XCHG %AX,%AX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SUB $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RDX,(%RDI) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM0,-0x8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM6,-0x10(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 40fdd0 <log> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| VMULSD 0x15ec1(%RIP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VDIVSD -0x8(%RBP),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VSQRTSD %XMM0,%XMM0,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VMULSD -0x10(%RBP),%XMM0,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| NOPL (%RAX,%RAX,1) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼gasdev– | 0.01 | 0 |
| ○Loop 91 - random.c:27-48 - exec | 0.01 | 0 |
