| Function: gasdev | Module: exec | Source: random.c:22-48 [...] | Coverage: 0.03% |
|---|
| Function: gasdev | Module: exec | Source: random.c:22-48 [...] | Coverage: 0.03% |
|---|
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/random.c: 22 - 48 |
-------------------------------------------------------------------------------- |
22: { |
23: real_t rsq,v1,v2; |
24: do |
25: { |
26: v1 = 2.0*lcg61(seed)-1.0; |
27: v2 = 2.0*lcg61(seed)-1.0; |
28: rsq = v1*v1+v2*v2; |
29: } while (rsq >= 1.0 || rsq == 0.0); |
30: |
31: return v2 * sqrt(-2.0*log(rsq)/rsq); |
32: } |
[...] |
45: *seed *= UINT64_C(437799614237992725); |
46: *seed %= UINT64_C(2305843009213693951); |
47: |
48: return *seed*convertToDouble; |
0x40ecb0 PUSH %RBP |
0x40ecb1 MOV %RDI,%R8 |
0x40ecb4 VXORPS %XMM5,%XMM5,%XMM5 |
0x40ecb8 MOV $0x9,%ESI |
0x40ecbd VXORPD %XMM7,%XMM7,%XMM7 |
0x40ecc1 MOV %RSP,%RBP |
0x40ecc4 SUB $0x10,%RSP |
0x40ecc8 VMOVSD 0x2f18(%RIP),%XMM4 |
0x40ecd0 VMOVSD 0x2ff0(%RIP),%XMM3 |
0x40ecd8 VMOVSD 0x2fe0(%RIP),%XMM6 |
0x40ece0 MOV (%RDI),%RCX |
0x40ece3 MOV $0x613606df9756715,%RDI |
0x40eced NOPL (%RAX) |
(92) 0x40ecf0 IMUL %RDI,%RCX |
(92) 0x40ecf4 MOV %RCX,%RAX |
(92) 0x40ecf7 MOV %RCX,%R9 |
(92) 0x40ecfa MUL %RSI |
(92) 0x40ecfd SUB %RDX,%R9 |
(92) 0x40ed00 SHR $0x1,%R9 |
(92) 0x40ed03 ADD %R9,%RDX |
(92) 0x40ed06 SHR $0x3c,%RDX |
(92) 0x40ed0a MOV %RDX,%R10 |
(92) 0x40ed0d SAL $0x3d,%R10 |
(92) 0x40ed11 SUB %RDX,%R10 |
(92) 0x40ed14 SUB %R10,%RCX |
(92) 0x40ed17 VCVTSI2SD %RCX,%XMM5,%XMM0 |
(92) 0x40ed1c IMUL %RDI,%RCX |
(92) 0x40ed20 MOV %RCX,%RAX |
(92) 0x40ed23 VFMADD132SD %XMM4,%XMM3,%XMM0 |
(92) 0x40ed28 MOV %RCX,%R11 |
(92) 0x40ed2b MUL %RSI |
(92) 0x40ed2e SUB %RDX,%R11 |
(92) 0x40ed31 SHR $0x1,%R11 |
(92) 0x40ed34 ADD %R11,%RDX |
(92) 0x40ed37 SHR $0x3c,%RDX |
(92) 0x40ed3b MOV %RDX,%R9 |
(92) 0x40ed3e SAL $0x3d,%R9 |
(92) 0x40ed42 SUB %RDX,%R9 |
(92) 0x40ed45 SUB %R9,%RCX |
(92) 0x40ed48 VCVTSI2SD %RCX,%XMM5,%XMM2 |
(92) 0x40ed4d VFMADD132SD %XMM4,%XMM3,%XMM2 |
(92) 0x40ed52 VMULSD %XMM2,%XMM2,%XMM1 |
(92) 0x40ed56 VFMADD231SD %XMM0,%XMM0,%XMM1 |
(92) 0x40ed5b VCOMISD %XMM6,%XMM1 |
(92) 0x40ed5f JAE 40ecf0 |
(92) 0x40ed61 VCOMISD %XMM7,%XMM1 |
(92) 0x40ed65 JE 40ecf0 |
0x40ed67 MOV %RCX,(%R8) |
0x40ed6a VMOVSD %XMM1,%XMM1,%XMM0 |
0x40ed6e VMOVSD %XMM2,-0x10(%RBP) |
0x40ed73 VMOVSD %XMM1,-0x8(%RBP) |
0x40ed78 CALL 403140 <log@plt> |
0x40ed7d VMOVSD -0x8(%RBP),%XMM9 |
0x40ed82 VMOVSD -0x10(%RBP),%XMM11 |
0x40ed87 VMULSD 0x2ec9(%RIP),%XMM0,%XMM8 |
0x40ed8f LEAVE |
0x40ed90 VDIVSD %XMM9,%XMM8,%XMM10 |
0x40ed95 VSQRTSD %XMM10,%XMM10,%XMM10 |
0x40ed9a VMULSD %XMM11,%XMM10,%XMM0 |
0x40ed9f RET |
| Path / |
| Source file and lines | random.c:22-48 |
| Module | exec |
| nb instructions | 26 |
| nb uops | 29 |
| loop length | 121 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 12 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 4.83 cycles |
| front end | 4.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.20 | 2.20 | 3.00 | 3.00 | 2.50 | 2.20 | 2.20 | 2.50 | 2.50 | 2.50 | 2.20 | 3.00 |
| cycles | 2.20 | 2.20 | 3.00 | 3.00 | 2.50 | 2.20 | 2.20 | 2.50 | 2.50 | 2.50 | 2.20 | 3.00 |
| Cycles executing div or sqrt instructions | 8.50 |
| FE+BE cycles | 9.42-9.37 |
| Stall cycles | 3.90-3.85 |
| ROB full (events) | 4.50-4.46 |
| Front-end | 4.83 |
| Dispatch | 3.00 |
| DIV/SQRT | 8.50 |
| Overall L1 | 8.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 66% |
| all | 11% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 50% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 6% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 20% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VXORPS %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SUB $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD 0x2f18(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x2ff0(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x2fe0(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV (%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV $0x613606df9756715,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV %RCX,(%R8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM1,%XMM1,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD %XMM2,-0x10(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM1,-0x8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 403140 <log@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| VMOVSD -0x8(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD -0x10(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD 0x2ec9(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| LEAVE | 3 | 0.60 | 0.60 | 0.33 | 0.33 | 0 | 0.60 | 0.60 | 0 | 0 | 0 | 0.60 | 0.33 | 2-6 | 2 |
| VDIVSD %XMM9,%XMM8,%XMM10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VSQRTSD %XMM10,%XMM10,%XMM10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VMULSD %XMM11,%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| Source file and lines | random.c:22-48 |
| Module | exec |
| nb instructions | 26 |
| nb uops | 29 |
| loop length | 121 |
| used x86 registers | 7 |
| used mmx registers | 0 |
| used xmm registers | 12 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 2 |
| micro-operation queue | 4.83 cycles |
| front end | 4.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 2.20 | 2.20 | 3.00 | 3.00 | 2.50 | 2.20 | 2.20 | 2.50 | 2.50 | 2.50 | 2.20 | 3.00 |
| cycles | 2.20 | 2.20 | 3.00 | 3.00 | 2.50 | 2.20 | 2.20 | 2.50 | 2.50 | 2.50 | 2.20 | 3.00 |
| Cycles executing div or sqrt instructions | 8.50 |
| FE+BE cycles | 9.42-9.37 |
| Stall cycles | 3.90-3.85 |
| ROB full (events) | 4.50-4.46 |
| Front-end | 4.83 |
| Dispatch | 3.00 |
| DIV/SQRT | 8.50 |
| Overall L1 | 8.50 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 14% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 66% |
| all | 11% |
| load | 0% |
| store | 0% |
| mul | 0% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 0% |
| other | 50% |
| all | 10% |
| load | 12% |
| store | 12% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 6% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 20% |
| all | 13% |
| load | 12% |
| store | 12% |
| mul | 12% |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | 12% |
| other | 17% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RDI,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VXORPS %XMM5,%XMM5,%XMM5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV $0x9,%ESI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| VXORPD %XMM7,%XMM7,%XMM7 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SUB $0x10,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMOVSD 0x2f18(%RIP),%XMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x2ff0(%RIP),%XMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x2fe0(%RIP),%XMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV (%RDI),%RCX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV $0x613606df9756715,%RDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.28 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV %RCX,(%R8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM1,%XMM1,%XMM0 | 1 | 0.33 | 0.33 | 0 | 0 | 0 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| VMOVSD %XMM2,-0x10(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVSD %XMM1,-0x8(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| CALL 403140 <log@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| VMOVSD -0x8(%RBP),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD -0x10(%RBP),%XMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD 0x2ec9(%RIP),%XMM0,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| LEAVE | 3 | 0.60 | 0.60 | 0.33 | 0.33 | 0 | 0.60 | 0.60 | 0 | 0 | 0 | 0.60 | 0.33 | 2-6 | 2 |
| VDIVSD %XMM9,%XMM8,%XMM10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| VSQRTSD %XMM10,%XMM10,%XMM10 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-19 | 4.50 |
| VMULSD %XMM11,%XMM10,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| RET | 1 | 0.50 | 0 | 0.33 | 0.33 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0.33 | 0 | 2.13 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼gasdev– | 0.03 | 0 |
| ○Loop 92 - random.c:26-48 - exec | 0.02 | 0 |
