| Function: setVcm.extracted | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.03% |
|---|
| Function: setVcm.extracted | Module: exec | Source: initAtoms.c:123-133 | Coverage: 0.03% |
|---|
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/initAtoms.c: 123 - 133 |
-------------------------------------------------------------------------------- |
123: #pragma omp parallel for |
124: for (int iBox=0; iBox<s->boxes->nLocalBoxes; ++iBox) |
125: { |
126: for (int iOff=MAXATOMS*iBox, ii=0; ii<s->boxes->nAtoms[iBox]; ++ii, ++iOff) |
127: { |
128: int iSpecies = s->atoms->iSpecies[iOff]; |
129: real_t mass = s->species[iSpecies].mass; |
130: |
131: s->atoms->p[iOff][0] += mass * vShift[0]; |
132: s->atoms->p[iOff][1] += mass * vShift[1]; |
133: s->atoms->p[iOff][2] += mass * vShift[2]; |
0x4090b0 PUSH %RBP |
0x4090b1 MOV %RSP,%RBP |
0x4090b4 PUSH %R15 |
0x4090b6 PUSH %R14 |
0x4090b8 PUSH %R13 |
0x4090ba PUSH %R12 |
0x4090bc PUSH %RBX |
0x4090bd SUB $0x28,%RSP |
0x4090c1 MOV %RCX,-0x50(%RBP) |
0x4090c5 MOV %RDX,-0x48(%RBP) |
0x4090c9 MOVL $0,-0x3c(%RBP) |
0x4090d0 MOV (%RDI),%ESI |
0x4090d2 MOVL $0,-0x30(%RBP) |
0x4090d9 MOV %R9D,-0x2c(%RBP) |
0x4090dd MOVL $0x1,-0x38(%RBP) |
0x4090e4 SUB $0x8,%RSP |
0x4090e8 LEA -0x38(%RBP),%RAX |
0x4090ec LEA -0x3c(%RBP),%RCX |
0x4090f0 LEA -0x30(%RBP),%R8 |
0x4090f4 LEA -0x2c(%RBP),%R9 |
0x4090f8 MOV $0x42e490,%EDI |
0x4090fd MOV %ESI,-0x34(%RBP) |
0x409100 MOV $0x22,%EDX |
0x409105 PUSH $0x1 |
0x409107 PUSH $0x1 |
0x409109 PUSH %RAX |
0x40910a CALL 403230 <__kmpc_for_static_init_4@plt> |
0x40910f ADD $0x20,%RSP |
0x409113 MOV -0x30(%RBP),%EAX |
0x409116 MOV -0x2c(%RBP),%ECX |
0x409119 CMP %ECX,%EAX |
0x40911b JBE 40913b |
0x40911d MOV $0x42e4b0,%EDI |
0x409122 MOV -0x34(%RBP),%ESI |
0x409125 ADD $0x28,%RSP |
0x409129 POP %RBX |
0x40912a POP %R12 |
0x40912c POP %R13 |
0x40912e POP %R14 |
0x409130 POP %R15 |
0x409132 POP %RBP |
0x409133 VZEROUPPER |
0x409136 JMP 4030f0 |
0x40913b MOV -0x48(%RBP),%RDX |
0x40913f MOV 0x18(%RDX),%RDX |
0x409143 MOV 0x78(%RDX),%R14 |
0x409147 SUB %RAX,%RCX |
0x40914a MOV %EAX,%ESI |
0x40914c SAL $0x6,%ESI |
0x40914f XOR %EDI,%EDI |
0x409151 VBROADCASTF128 0x1a246(%RIP),%YMM0 |
0x40915a VMOVUPD 0x1a19e(%RIP),%YMM1 |
0x409162 VMOVUPD 0x1a1b6(%RIP),%YMM2 |
0x40916a VMOVUPD 0x1a1ce(%RIP),%YMM3 |
0x409172 VMOVUPD 0x1a1e6(%RIP),%YMM4 |
0x40917a JMP 40918f |
0x40917c NOPL (%RAX) |
(62) 0x409180 LEA 0x1(%RDI),%RDX |
(62) 0x409184 ADD $0x40,%ESI |
(62) 0x409187 CMP %RCX,%RDI |
(62) 0x40918a MOV %RDX,%RDI |
(62) 0x40918d JE 40911d |
(62) 0x40918f MOV %ESI,%ESI |
(62) 0x409191 LEA (%RDI,%RAX,1),%RDX |
(62) 0x409195 MOV (%R14,%RDX,4),%R8D |
(62) 0x409199 TEST %R8D,%R8D |
(62) 0x40919c JLE 409180 |
(62) 0x40919e MOV -0x48(%RBP),%R9 |
(62) 0x4091a2 MOV 0x20(%R9),%RDX |
(62) 0x4091a6 MOV 0x28(%R9),%R9 |
(62) 0x4091aa MOV 0x10(%RDX),%R10 |
(62) 0x4091ae MOV 0x20(%RDX),%R11 |
(62) 0x4091b2 MOV -0x50(%RBP),%RDX |
(62) 0x4091b6 VMOVUPD (%RDX),%XMM5 |
(62) 0x4091ba VMOVSD 0x10(%RDX),%XMM6 |
(62) 0x4091bf MOV %R8D,%R12D |
(62) 0x4091c2 AND $-0x4,%R12D |
(62) 0x4091c6 JE 4092e0 |
(62) 0x4091cc LEA (,%RSI,8),%RDX |
(62) 0x4091d4 LEA (%RDX,%RDX,2),%R13 |
(62) 0x4091d8 LEA (,%RSI,4),%R15 |
(62) 0x4091e0 LEA -0x1(%R12),%EDX |
(62) 0x4091e5 VBROADCASTSD %XMM5,%YMM7 |
(62) 0x4091ea VXORPS %XMM8,%XMM8,%XMM8 |
(62) 0x4091ef VPERMPD $0x55,%YMM5,%YMM8 |
(62) 0x4091f5 VBROADCASTSD %XMM6,%YMM9 |
(62) 0x4091fa ADD %R11,%R13 |
(62) 0x4091fd ADD %R10,%R15 |
(62) 0x409200 XOR %EBX,%EBX |
(62) 0x409202 NOPW %CS:(%RAX,%RAX,1) |
(64) 0x409210 VPMOVSXDQ (%R15,%RBX,4),%YMM10 |
(64) 0x409216 KXNORW %K0,%K0,%K1 |
(64) 0x40921a VXORPD %XMM11,%XMM11,%XMM11 |
(64) 0x40921f VPSLLQ $0x4,%YMM10,%YMM10 |
(64) 0x409225 VGATHERQPD 0x8(%R9,%YMM10,1),%YMM11{%K1} |
(64) 0x40922d VMOVUPD 0x20(%R13),%YMM10 |
(64) 0x409233 VBLENDPD $0x3,(%R13),%YMM10,%YMM12 |
(64) 0x40923a VMOVUPD 0x10(%R13),%XMM13 |
(64) 0x409240 VINSERTF128 $0x1,0x40(%R13),%YMM13,%YMM13 |
(64) 0x409247 VMOVUPD 0x20(%R13),%XMM14 |
(64) 0x40924d VBLENDPD $0xc,0x40(%R13),%YMM14,%YMM14 |
(64) 0x409254 VBROADCASTSD 0x50(%R13),%YMM15 |
(64) 0x40925a VSHUFPD $0x5,%YMM10,%YMM12,%YMM10 |
(64) 0x409260 VBLENDPD $0xa,%YMM13,%YMM12,%YMM12 |
(64) 0x409266 VBLENDPD $0x8,%YMM15,%YMM10,%YMM10 |
(64) 0x40926c VFMADD231PD %YMM11,%YMM7,%YMM12 |
(64) 0x409271 VFMADD231PD %YMM11,%YMM8,%YMM10 |
(64) 0x409276 VBLENDPD $0xa,%YMM14,%YMM13,%YMM13 |
(64) 0x40927c VFMADD231PD %YMM11,%YMM9,%YMM13 |
(64) 0x409281 VMOVAPD %YMM10,%YMM11 |
(64) 0x409286 VPERMT2PD %YMM12,%YMM0,%YMM11 |
(64) 0x40928c VMOVAPD %YMM10,%YMM14 |
(64) 0x409291 VPERMT2PD %YMM12,%YMM1,%YMM14 |
(64) 0x409297 VPERMT2PD %YMM10,%YMM2,%YMM12 |
(64) 0x40929d VPERMT2PD %YMM13,%YMM3,%YMM12 |
(64) 0x4092a3 VBLENDPD $0x2,%YMM13,%YMM14,%YMM10 |
(64) 0x4092a9 VPERMT2PD %YMM11,%YMM4,%YMM13 |
(64) 0x4092af VMOVUPD %YMM10,0x20(%R13) |
(64) 0x4092b5 VMOVUPD %YMM13,0x40(%R13) |
(64) 0x4092bb VMOVUPD %YMM12,(%R13) |
(64) 0x4092c1 ADD $0x60,%R13 |
(64) 0x4092c5 ADD $0x4,%RBX |
(64) 0x4092c9 CMP %EDX,%EBX |
(64) 0x4092cb JLE 409210 |
(62) 0x4092d1 CMP %R12D,%R8D |
(62) 0x4092d4 JE 409180 |
(62) 0x4092da JMP 4092e3 |
0x4092dc NOPL (%RAX) |
(62) 0x4092e0 XOR %R12D,%R12D |
(62) 0x4092e3 SUB %R12D,%R8D |
(62) 0x4092e6 MOVSXD %R12D,%RBX |
(62) 0x4092e9 ADD %RSI,%RBX |
(62) 0x4092ec LEA (%RBX,%RBX,2),%RDX |
(62) 0x4092f0 LEA 0x10(%R11,%RDX,8),%RDX |
(62) 0x4092f5 LEA (%R10,%RBX,4),%R10 |
(62) 0x4092f9 XOR %R11D,%R11D |
(62) 0x4092fc NOPL (%RAX) |
(63) 0x409300 MOVSXD (%R10,%R11,4),%RBX |
(63) 0x409304 SAL $0x4,%RBX |
(63) 0x409308 VMOVDDUP 0x8(%R9,%RBX,1),%XMM7 |
(63) 0x40930f VMOVAPD %XMM7,%XMM8 |
(63) 0x409313 VFMADD213PD -0x10(%RDX),%XMM5,%XMM8 |
(63) 0x409319 VMOVUPD %XMM8,-0x10(%RDX) |
(63) 0x40931e VMOVSD (%RDX),%XMM8 |
(63) 0x409322 VFMADD231SD %XMM7,%XMM6,%XMM8 |
(63) 0x409327 VMOVSD %XMM8,(%RDX) |
(63) 0x40932b INC %R11 |
(63) 0x40932e ADD $0x18,%RDX |
(63) 0x409332 CMP %R11D,%R8D |
(63) 0x409335 JNE 409300 |
(62) 0x409337 JMP 409180 |
0x40933c NOPL (%RAX) |
| Path / |
| Source file and lines | initAtoms.c:123-133 |
| Module | exec |
| nb instructions | 59 |
| nb uops | 61 |
| loop length | 216 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 10.17 cycles |
| front end | 10.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.40 | 1.40 | 6.00 | 6.00 | 8.50 | 1.40 | 1.40 | 8.50 | 8.50 | 8.50 | 1.40 | 6.00 |
| cycles | 1.40 | 1.40 | 6.00 | 6.00 | 8.50 | 1.40 | 1.40 | 8.50 | 8.50 | 8.50 | 1.40 | 6.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 10.02-10.06 |
| Stall cycles | 0.00 |
| Front-end | 10.17 |
| Dispatch | 8.50 |
| Overall L1 | 10.17 |
| all | 5% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 26% |
| load | 62% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 40% |
| all | 9% |
| load | 8% |
| store | 8% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 45% |
| load | 45% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 17% |
| load | 31% |
| store | 8% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 13% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RCX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV $0x42e490,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| CALL 403230 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JBE 40913b <setVcm.extracted+0x8b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| MOV $0x42e4b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JMP 4030f0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x18(%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x78(%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VBROADCASTF128 0x1a246(%RIP),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 5-8 | 0.33 |
| VMOVUPD 0x1a19e(%RIP),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1b6(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1ce(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1e6(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| JMP 40918f <setVcm.extracted+0xdf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Source file and lines | initAtoms.c:123-133 |
| Module | exec |
| nb instructions | 59 |
| nb uops | 61 |
| loop length | 216 |
| used x86 registers | 14 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 5 |
| used zmm registers | 0 |
| nb stack references | 7 |
| micro-operation queue | 10.17 cycles |
| front end | 10.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.40 | 1.40 | 6.00 | 6.00 | 8.50 | 1.40 | 1.40 | 8.50 | 8.50 | 8.50 | 1.40 | 6.00 |
| cycles | 1.40 | 1.40 | 6.00 | 6.00 | 8.50 | 1.40 | 1.40 | 8.50 | 8.50 | 8.50 | 1.40 | 6.00 |
| Cycles executing div or sqrt instructions | NA |
| FE+BE cycles | 10.02-10.06 |
| Stall cycles | 0.00 |
| Front-end | 10.17 |
| Dispatch | 8.50 |
| Overall L1 | 10.17 |
| all | 5% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 25% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 26% |
| load | 62% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 40% |
| all | 9% |
| load | 8% |
| store | 8% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 10% |
| all | 45% |
| load | 45% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| all | 17% |
| load | 31% |
| store | 8% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 13% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| PUSH %RBP | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| MOV %RSP,%RBP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| PUSH %R15 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R14 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R13 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %R12 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RBX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| SUB $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RCX,-0x50(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RDX,-0x48(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOVL $0,-0x3c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%RDI),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOVL $0,-0x30(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %R9D,-0x2c(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOVL $0x1,-0x38(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| SUB $0x8,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| LEA -0x38(%RBP),%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x3c(%RBP),%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x30(%RBP),%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| LEA -0x2c(%RBP),%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| MOV $0x42e490,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %ESI,-0x34(%RBP) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV $0x22,%EDX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH $0x1 | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| PUSH %RAX | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 5-12 | 0.50 |
| CALL 403230 <__kmpc_for_static_init_4@plt> | 2 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0 | 1 |
| ADD $0x20,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x30(%RBP),%EAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x2c(%RBP),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| CMP %ECX,%EAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JBE 40913b <setVcm.extracted+0x8b> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| MOV $0x42e4b0,%EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV -0x34(%RBP),%ESI | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| ADD $0x28,%RSP | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| POP %RBX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| POP %RBP | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1-6 | 0.33 |
| VZEROUPPER | 2 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
| JMP 4030f0 <__kmpc_for_static_fini@plt> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2.08 |
| MOV -0x48(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x18(%RDX),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV 0x78(%RDX),%R14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| SUB %RAX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %EAX,%ESI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| SAL $0x6,%ESI | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0-2 | 0.50 |
| XOR %EDI,%EDI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| VBROADCASTF128 0x1a246(%RIP),%YMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 5-8 | 0.33 |
| VMOVUPD 0x1a19e(%RIP),%YMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1b6(%RIP),%YMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1ce(%RIP),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPD 0x1a1e6(%RIP),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| JMP 40918f <setVcm.extracted+0xdf> | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 5.84 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| NOPL (%RAX) | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.17 |
| Name | Coverage (%) | Time (s) |
|---|---|---|
| ▼setVcm.extracted– | 0.03 | 0 |
| ▼Loop 62 - initAtoms.c:123-133 - exec– | 0 | 0 |
| ○Loop 64 - initAtoms.c:126-133 - exec | 0.03 | 0 |
| ○Loop 63 - initAtoms.c:126-133 - exec | 0 | 0 |
