| Loop Id: 45 | Module: exec | Source: haloExchange.c:380-389 | Coverage: 0.04% |
|---|
| Loop Id: 45 | Module: exec | Source: haloExchange.c:380-389 | Coverage: 0.04% |
|---|
0x4081a0 MOV (%R10,%R15,4),%ECX [3] |
0x4081a4 MOV %ECX,(%R13) [5] |
0x4081a8 MOV (%R11,%R15,4),%ECX [1] |
0x4081ac MOV %ECX,0x4(%R13) [5] |
0x4081b0 VADDPD -0x10(%RBX,%RDX,4),%XMM0,%XMM2 [4] |
0x4081b6 VMOVUPD %XMM2,0x8(%R13) [5] |
0x4081bc VADDSD (%RBX,%RDX,4),%XMM1,%XMM2 [4] |
0x4081c1 VMOVSD %XMM2,0x18(%R13) [5] |
0x4081c7 VMOVUPS -0x10(%R14,%RDX,4),%XMM2 [2] |
0x4081ce VMOVUPS %XMM2,0x20(%R13) [5] |
0x4081d4 VMOVSD (%R14,%RDX,4),%XMM2 [2] |
0x4081da VMOVSD %XMM2,0x30(%R13) [5] |
0x4081e0 INC %R15 |
0x4081e3 ADD $0x38,%R13 |
0x4081e7 INC %EDI |
0x4081e9 ADD $0x6,%RDX |
0x4081ed CMP %R12,%R15 |
0x4081f0 JL 4081a0 |
/home/eoseret/qaas_runs_CPU_9468/171-148-3214/intel/CoMD/build/CoMD/CoMD/src-openmp/haloExchange.c: 380 - 389 |
-------------------------------------------------------------------------------- |
380: for (int ii=iOff; ii<iOff+s->boxes->nAtoms[iBox]; ++ii) |
381: { |
382: buf[nBuf].gid = s->atoms->gid[ii]; |
383: buf[nBuf].type = s->atoms->iSpecies[ii]; |
384: buf[nBuf].rx = s->atoms->r[ii][0] + shift[0]; |
385: buf[nBuf].ry = s->atoms->r[ii][1] + shift[1]; |
386: buf[nBuf].rz = s->atoms->r[ii][2] + shift[2]; |
387: buf[nBuf].px = s->atoms->p[ii][0]; |
388: buf[nBuf].py = s->atoms->p[ii][1]; |
389: buf[nBuf].pz = s->atoms->p[ii][2]; |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.58 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 7.24 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | micro-operation queue, |
| Function | loadAtomsBuffer |
| Source | haloExchange.c:380-389 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.17 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 0.44 |
| Front-end cycles | 3.17 |
| DIV/SQRT cycles | 0.70 |
| P0 cycles | 1.00 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 3.00 |
| P4 cycles | 1.00 |
| P5 cycles | 0.70 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 0.60 |
| P10 cycles | 2.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.31 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 18.00 |
| Nb uops | 17.00 |
| Nb loads | 6.00 |
| Nb stores | 6.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.95 |
| Nb FLOP add-sub | 3.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 35.37 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 56.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 3.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 30.77 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 33.33 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 13.94 |
| Vector-efficiency ratio load | 14.58 |
| Vector-efficiency ratio store | 14.58 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 14.58 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.58 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 7.24 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | micro-operation queue, |
| Function | loadAtomsBuffer |
| Source | haloExchange.c:380-389 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 3.17 |
| CQA cycles if no scalar integer | 2.00 |
| CQA cycles if FP arith vectorized | 3.00 |
| CQA cycles if fully vectorized | 0.44 |
| Front-end cycles | 3.17 |
| DIV/SQRT cycles | 0.70 |
| P0 cycles | 1.00 |
| P1 cycles | 2.00 |
| P2 cycles | 2.00 |
| P3 cycles | 3.00 |
| P4 cycles | 1.00 |
| P5 cycles | 0.70 |
| P6 cycles | 3.00 |
| P7 cycles | 3.00 |
| P8 cycles | 3.00 |
| P9 cycles | 0.60 |
| P10 cycles | 2.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 3.31 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 18.00 |
| Nb uops | 17.00 |
| Nb loads | 6.00 |
| Nb stores | 6.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.95 |
| Nb FLOP add-sub | 3.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 35.37 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 56.00 |
| Bytes stored | 56.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 3.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 30.77 |
| Vectorization ratio load | 33.33 |
| Vectorization ratio store | 33.33 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 33.33 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 13.94 |
| Vector-efficiency ratio load | 14.58 |
| Vector-efficiency ratio store | 14.58 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 14.58 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | loadAtomsBuffer |
| Source file and lines | haloExchange.c:380-389 |
| Module | exec |
| nb instructions | 18 |
| nb uops | 17 |
| loop length | 82 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 3.17 cycles |
| front end | 3.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.70 | 1.00 | 2.00 | 2.00 | 3.00 | 1.00 | 0.70 | 3.00 | 3.00 | 3.00 | 0.60 | 2.00 |
| cycles | 0.70 | 1.00 | 2.00 | 2.00 | 3.00 | 1.00 | 0.70 | 3.00 | 3.00 | 3.00 | 0.60 | 2.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.31 |
| Stall cycles | 0.00 |
| Front-end | 3.17 |
| Dispatch | 3.00 |
| Data deps. | 1.00 |
| Overall L1 | 3.17 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 30% |
| load | 33% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 6% |
| load | 6% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 18% |
| load | 18% |
| store | 18% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 14% |
| store | 14% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 14% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV (%R10,%R15,4),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %ECX,(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R11,%R15,4),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %ECX,0x4(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDPD -0x10(%RBX,%RDX,4),%XMM0,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %XMM2,0x8(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VADDSD (%RBX,%RDX,4),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM2,0x18(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPS -0x10(%R14,%RDX,4),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPS %XMM2,0x20(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD (%R14,%RDX,4),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD %XMM2,0x30(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| ADD $0x38,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| ADD $0x6,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JL 4081a0 <loadAtomsBuffer+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | loadAtomsBuffer |
| Source file and lines | haloExchange.c:380-389 |
| Module | exec |
| nb instructions | 18 |
| nb uops | 17 |
| loop length | 82 |
| used x86 registers | 10 |
| used mmx registers | 0 |
| used xmm registers | 3 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 3.17 cycles |
| front end | 3.17 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.70 | 1.00 | 2.00 | 2.00 | 3.00 | 1.00 | 0.70 | 3.00 | 3.00 | 3.00 | 0.60 | 2.00 |
| cycles | 0.70 | 1.00 | 2.00 | 2.00 | 3.00 | 1.00 | 0.70 | 3.00 | 3.00 | 3.00 | 0.60 | 2.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 3.31 |
| Stall cycles | 0.00 |
| Front-end | 3.17 |
| Dispatch | 3.00 |
| Data deps. | 1.00 |
| Overall L1 | 3.17 |
| all | 0% |
| load | 0% |
| store | 0% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 30% |
| load | 33% |
| store | 33% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 33% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 6% |
| load | 6% |
| store | 6% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 6% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 18% |
| load | 18% |
| store | 18% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 18% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 13% |
| load | 14% |
| store | 14% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 14% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV (%R10,%R15,4),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %ECX,(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV (%R11,%R15,4),%ECX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV %ECX,0x4(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VADDPD -0x10(%RBX,%RDX,4),%XMM0,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %XMM2,0x8(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VADDSD (%RBX,%RDX,4),%XMM1,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM2,0x18(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VMOVUPS -0x10(%R14,%RDX,4),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VMOVUPS %XMM2,0x20(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVSD (%R14,%RDX,4),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD %XMM2,0x30(%R13) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| INC %R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| ADD $0x38,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| INC %EDI | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| ADD $0x6,%RDX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP %R12,%R15 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JL 4081a0 <loadAtomsBuffer+0xc0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
