| Loop Id: 12 | Module: exec | Source: stream.c:476-479 | Coverage: 0.13% |
|---|
| Loop Id: 12 | Module: exec | Source: stream.c:476-479 | Coverage: 0.13% |
|---|
0x4021a0 VMOVUPD 0xc0(%RBX,%RAX,8),%ZMM6 [1] |
0x4021a8 VMOVUPD 0x100(%RBX,%RAX,8),%ZMM7 [1] |
0x4021b0 VMOVUPD 0x140(%RBX,%RAX,8),%ZMM8 [1] |
0x4021b8 VSUBPD %ZMM1,%ZMM6,%ZMM6 |
0x4021be VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x4021c4 VADDPD %ZMM5,%ZMM6,%ZMM5 |
0x4021ca VMOVUPD 0xc0(%R12,%RAX,8),%ZMM6 [1] |
0x4021d2 VMOVUPD 0x100(%R12,%RAX,8),%ZMM9 [1] |
0x4021da VMOVUPD 0x140(%R12,%RAX,8),%ZMM10 [1] |
0x4021e2 VSUBPD %ZMM2,%ZMM6,%ZMM6 |
0x4021e8 VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x4021ee VADDPD %ZMM4,%ZMM6,%ZMM4 |
0x4021f4 VMOVUPD 0xc0(%R14,%RAX,8),%ZMM6 [1] |
0x4021fc VMOVUPD 0x100(%R14,%RAX,8),%ZMM11 [1] |
0x402204 VMOVUPD 0x140(%R14,%RAX,8),%ZMM12 [1] |
0x40220c VSUBPD %ZMM3,%ZMM6,%ZMM6 |
0x402212 VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x402218 VADDPD %ZMM0,%ZMM6,%ZMM0 |
0x40221e VSUBPD %ZMM1,%ZMM7,%ZMM6 |
0x402224 VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x40222a VSUBPD %ZMM2,%ZMM9,%ZMM7 |
0x402230 VANDPD %ZMM13,%ZMM7,%ZMM7 |
0x402236 VSUBPD %ZMM3,%ZMM11,%ZMM9 |
0x40223c VANDPD %ZMM13,%ZMM9,%ZMM9 |
0x402242 VSUBPD %ZMM1,%ZMM8,%ZMM8 |
0x402248 VANDPD %ZMM13,%ZMM8,%ZMM8 |
0x40224e VADDPD %ZMM6,%ZMM8,%ZMM6 |
0x402254 VADDPD %ZMM5,%ZMM6,%ZMM5 |
0x40225a VSUBPD %ZMM2,%ZMM10,%ZMM6 |
0x402260 VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x402266 VADDPD %ZMM7,%ZMM6,%ZMM6 |
0x40226c VADDPD %ZMM4,%ZMM6,%ZMM4 |
0x402272 VSUBPD %ZMM3,%ZMM12,%ZMM6 |
0x402278 VANDPD %ZMM13,%ZMM6,%ZMM6 |
0x40227e VADDPD %ZMM9,%ZMM6,%ZMM6 |
0x402284 VADDPD %ZMM0,%ZMM6,%ZMM0 |
0x40228a ADD $0x18,%RAX |
0x40228e CMP $0x3344ffe8,%RAX |
0x402294 JB 4021a0 |
/home/eoseret/qaas_runs_CPU_9468/171-111-6305/intel/stream/build/stream/src/stream.c: 476 - 479 |
-------------------------------------------------------------------------------- |
476: for (j=0; j<STREAM_ARRAY_SIZE; j++) { |
477: aSumErr += abs(a[j] - aj); |
478: bSumErr += abs(b[j] - bj); |
479: cSumErr += abs(c[j] - cj); |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P0, P5, |
| Function | main |
| Source | stream.c:476-479 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.50 |
| CQA cycles if no scalar integer | 13.50 |
| CQA cycles if FP arith vectorized | 13.50 |
| CQA cycles if fully vectorized | 13.50 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 13.50 |
| P0 cycles | 9.00 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.50 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 6 |
| FE+BE cycles (UFS) | 13.66 |
| Stall cycles (UFS) | 6.82 |
| Nb insns | 39.00 |
| Nb uops | 38.00 |
| Nb loads | 9.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 10.67 |
| Nb FLOP add-sub | 144.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 42.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 576.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 1.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.50 |
| Bottlenecks | P0, P5, |
| Function | main |
| Source | stream.c:476-479 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 13.50 |
| CQA cycles if no scalar integer | 13.50 |
| CQA cycles if FP arith vectorized | 13.50 |
| CQA cycles if fully vectorized | 13.50 |
| Front-end cycles | 6.33 |
| DIV/SQRT cycles | 13.50 |
| P0 cycles | 9.00 |
| P1 cycles | 3.00 |
| P2 cycles | 3.00 |
| P3 cycles | 0.00 |
| P4 cycles | 13.50 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 3.00 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 6 |
| FE+BE cycles (UFS) | 13.66 |
| Stall cycles (UFS) | 6.82 |
| Nb insns | 39.00 |
| Nb uops | 38.00 |
| Nb loads | 9.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 10.67 |
| Nb FLOP add-sub | 144.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 42.67 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 576.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 100.00 |
| Vector-efficiency ratio all | 100.00 |
| Vector-efficiency ratio load | 100.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 100.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 100.00 |
| Path / |
| Function | main |
| Source file and lines | stream.c:476-479 |
| Module | exec |
| nb instructions | 39 |
| nb uops | 38 |
| loop length | 250 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 0 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.50 | 0.00 | 3.00 | 3.00 | 0.00 | 13.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.00 |
| cycles | 13.50 | 9.00 | 3.00 | 3.00 | 0.00 | 13.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 6.00 |
| FE+BE cycles | 13.66 |
| Stall cycles | 6.82 |
| RS full (events) | 12.85 |
| Front-end | 6.33 |
| Dispatch | 13.50 |
| Data deps. | 6.00 |
| Overall L1 | 13.50 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD 0xc0(%RBX,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%RBX,%RAX,8),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%RBX,%RAX,8),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM1,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD 0xc0(%R12,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%R12,%RAX,8),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%R12,%RAX,8),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM2,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM4,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD 0xc0(%R14,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%R14,%RAX,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%R14,%RAX,8),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM3,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM1,%ZMM7,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM2,%ZMM9,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM3,%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM1,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM6,%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM2,%ZMM10,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM7,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM4,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM3,%ZMM12,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM9,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP $0x3344ffe8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 4021a0 <main+0xfe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | main |
| Source file and lines | stream.c:476-479 |
| Module | exec |
| nb instructions | 39 |
| nb uops | 38 |
| loop length | 250 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 0 |
| used zmm registers | 14 |
| nb stack references | 0 |
| micro-operation queue | 6.33 cycles |
| front end | 6.33 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 13.50 | 0.00 | 3.00 | 3.00 | 0.00 | 13.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.00 |
| cycles | 13.50 | 9.00 | 3.00 | 3.00 | 0.00 | 13.50 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 3.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 6.00 |
| FE+BE cycles | 13.66 |
| Stall cycles | 6.82 |
| RS full (events) | 12.85 |
| Front-end | 6.33 |
| Dispatch | 13.50 |
| Data deps. | 6.00 |
| Overall L1 | 13.50 |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| all | 100% |
| load | 100% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 100% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD 0xc0(%RBX,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%RBX,%RAX,8),%ZMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%RBX,%RAX,8),%ZMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM1,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD 0xc0(%R12,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%R12,%RAX,8),%ZMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%R12,%RAX,8),%ZMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM2,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM4,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMOVUPD 0xc0(%R14,%RAX,8),%ZMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x100(%R14,%RAX,8),%ZMM11 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VMOVUPD 0x140(%R14,%RAX,8),%ZMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.50 |
| VSUBPD %ZMM3,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM1,%ZMM7,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM2,%ZMM9,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM7,%ZMM7 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM3,%ZMM11,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM9,%ZMM9 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VSUBPD %ZMM1,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM8,%ZMM8 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM6,%ZMM8,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM5,%ZMM6,%ZMM5 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM2,%ZMM10,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM7,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM4,%ZMM6,%ZMM4 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBPD %ZMM3,%ZMM12,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VANDPD %ZMM13,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDPD %ZMM9,%ZMM6,%ZMM6 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDPD %ZMM0,%ZMM6,%ZMM0 | 1 | 0.50 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| ADD $0x18,%RAX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| CMP $0x3344ffe8,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JB 4021a0 <main+0xfe0> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
