| Loop Id: 4 | Module: exec | Source: stream.c:344-344 | Coverage: 28.94% |
|---|
| Loop Id: 4 | Module: exec | Source: stream.c:344-344 | Coverage: 28.94% |
|---|
0x402101 VMOVUPD (%R8,%RCX,1),%YMM14 [3] |
0x402107 VADDPD (%RBX,%RCX,1),%YMM14,%YMM15 [2] |
0x40210c VMOVUPD %YMM15,(%RSI,%RCX,1) [1] |
0x402111 VMOVUPD 0x20(%R8,%RCX,1),%YMM6 [3] |
0x402118 VADDPD 0x20(%RBX,%RCX,1),%YMM6,%YMM0 [2] |
0x40211e VMOVUPD %YMM0,0x20(%RSI,%RCX,1) [1] |
0x402124 VMOVUPD 0x40(%R8,%RCX,1),%YMM5 [3] |
0x40212b VADDPD 0x40(%RBX,%RCX,1),%YMM5,%YMM1 [2] |
0x402131 VMOVUPD %YMM1,0x40(%RSI,%RCX,1) [1] |
0x402137 VMOVUPD 0x60(%R8,%RCX,1),%YMM4 [3] |
0x40213e VADDPD 0x60(%RBX,%RCX,1),%YMM4,%YMM2 [2] |
0x402144 VMOVUPD %YMM2,0x60(%RSI,%RCX,1) [1] |
0x40214a VMOVUPD 0x80(%R8,%RCX,1),%YMM3 [3] |
0x402154 VADDPD 0x80(%RBX,%RCX,1),%YMM3,%YMM7 [2] |
0x40215d VMOVUPD %YMM7,0x80(%RSI,%RCX,1) [1] |
0x402166 VMOVUPD 0xa0(%R8,%RCX,1),%YMM8 [3] |
0x402170 VADDPD 0xa0(%RBX,%RCX,1),%YMM8,%YMM9 [2] |
0x402179 VMOVUPD %YMM9,0xa0(%RSI,%RCX,1) [1] |
0x402182 VMOVUPD 0xc0(%R8,%RCX,1),%YMM10 [3] |
0x40218c VADDPD 0xc0(%RBX,%RCX,1),%YMM10,%YMM11 [2] |
0x402195 VMOVUPD %YMM11,0xc0(%RSI,%RCX,1) [1] |
0x40219e VMOVUPD 0xe0(%R8,%RCX,1),%YMM12 [3] |
0x4021a8 VADDPD 0xe0(%RBX,%RCX,1),%YMM12,%YMM13 [2] |
0x4021b1 VMOVUPD %YMM13,0xe0(%RSI,%RCX,1) [1] |
0x4021ba ADD $0x100,%RCX |
0x4021c1 CMP %R13,%RCX |
0x4021c4 JNE 402101 |
/home/eoseret/qaas_runs_CPU_9468/171-111-6305/intel/stream/build/stream/src/stream.c: 344 - 344 |
-------------------------------------------------------------------------------- |
344: c[j] = a[j]+b[j]; |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | micro-operation queue, |
| Function | main._omp_fn.6 |
| Source | stream.c:344-344 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.67 |
| CQA cycles if no scalar integer | 5.67 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 2.83 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 0.70 |
| P0 cycles | 4.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 4.00 |
| P4 cycles | 4.00 |
| P5 cycles | 0.70 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.60 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 5.83 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 16.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 5.65 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 135.53 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.06 |
| CQA speedup if fully vectorized | 2.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.06 |
| Bottlenecks | micro-operation queue, |
| Function | main._omp_fn.6 |
| Source | stream.c:344-344 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.67 |
| CQA cycles if no scalar integer | 5.67 |
| CQA cycles if FP arith vectorized | 5.33 |
| CQA cycles if fully vectorized | 2.83 |
| Front-end cycles | 5.67 |
| DIV/SQRT cycles | 0.70 |
| P0 cycles | 4.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 4.00 |
| P4 cycles | 4.00 |
| P5 cycles | 0.70 |
| P6 cycles | 4.00 |
| P7 cycles | 4.00 |
| P8 cycles | 4.00 |
| P9 cycles | 0.60 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | 5.83 |
| Stall cycles (UFS) | 0.00 |
| Nb insns | 27.00 |
| Nb uops | 26.00 |
| Nb loads | 16.00 |
| Nb stores | 8.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 5.65 |
| Nb FLOP add-sub | 32.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 135.53 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 512.00 |
| Bytes stored | 256.00 |
| Stride 0 | 0.00 |
| Stride 1 | 3.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 100.00 |
| Vectorization ratio load | 100.00 |
| Vectorization ratio store | 100.00 |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 100.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 50.00 |
| Vector-efficiency ratio load | 50.00 |
| Vector-efficiency ratio store | 50.00 |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 50.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| Function | main._omp_fn.6 |
| Source file and lines | stream.c:344-344 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 201 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.70 | 4.00 | 5.33 | 5.33 | 4.00 | 4.00 | 0.70 | 4.00 | 4.00 | 4.00 | 0.60 | 5.33 |
| cycles | 0.70 | 4.00 | 5.33 | 5.33 | 4.00 | 4.00 | 0.70 | 4.00 | 4.00 | 4.00 | 0.60 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 5.83 |
| Stall cycles | 0.00 |
| Front-end | 5.67 |
| Dispatch | 5.33 |
| Data deps. | 1.00 |
| Overall L1 | 5.67 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R8,%RCX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RBX,%RCX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM15,(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R8,%RCX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%RBX,%RCX,1),%YMM6,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM0,0x20(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R8,%RCX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%RBX,%RCX,1),%YMM5,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM1,0x40(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R8,%RCX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%RBX,%RCX,1),%YMM4,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM2,0x60(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x80(%R8,%RCX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x80(%RBX,%RCX,1),%YMM3,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM7,0x80(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xa0(%R8,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xa0(%RBX,%RCX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM9,0xa0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xc0(%R8,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xc0(%RBX,%RCX,1),%YMM10,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM11,0xc0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xe0(%R8,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xe0(%RBX,%RCX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM13,0xe0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %R13,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 402101 <main._omp_fn.6+0x171> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | main._omp_fn.6 |
| Source file and lines | stream.c:344-344 |
| Module | exec |
| nb instructions | 27 |
| nb uops | 26 |
| loop length | 201 |
| used x86 registers | 5 |
| used mmx registers | 0 |
| used xmm registers | 0 |
| used ymm registers | 16 |
| used zmm registers | 0 |
| nb stack references | 0 |
| micro-operation queue | 5.67 cycles |
| front end | 5.67 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 0.70 | 4.00 | 5.33 | 5.33 | 4.00 | 4.00 | 0.70 | 4.00 | 4.00 | 4.00 | 0.60 | 5.33 |
| cycles | 0.70 | 4.00 | 5.33 | 5.33 | 4.00 | 4.00 | 0.70 | 4.00 | 4.00 | 4.00 | 0.60 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| FE+BE cycles | 5.83 |
| Stall cycles | 0.00 |
| Front-end | 5.67 |
| Dispatch | 5.33 |
| Data deps. | 1.00 |
| Overall L1 | 5.67 |
| all | 100% |
| load | 100% |
| store | 100% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 100% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 50% |
| load | 50% |
| store | 50% |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 50% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVUPD (%R8,%RCX,1),%YMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD (%RBX,%RCX,1),%YMM14,%YMM15 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM15,(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x20(%R8,%RCX,1),%YMM6 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x20(%RBX,%RCX,1),%YMM6,%YMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM0,0x20(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x40(%R8,%RCX,1),%YMM5 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x40(%RBX,%RCX,1),%YMM5,%YMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM1,0x40(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x60(%R8,%RCX,1),%YMM4 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x60(%RBX,%RCX,1),%YMM4,%YMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM2,0x60(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0x80(%R8,%RCX,1),%YMM3 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0x80(%RBX,%RCX,1),%YMM3,%YMM7 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM7,0x80(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xa0(%R8,%RCX,1),%YMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xa0(%RBX,%RCX,1),%YMM8,%YMM9 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM9,0xa0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xc0(%R8,%RCX,1),%YMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xc0(%RBX,%RCX,1),%YMM10,%YMM11 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM11,0xc0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| VMOVUPD 0xe0(%R8,%RCX,1),%YMM12 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0-1 | 0.33 |
| VADDPD 0xe0(%RBX,%RCX,1),%YMM12,%YMM13 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVUPD %YMM13,0xe0(%RSI,%RCX,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 0-1 | 0.50 |
| ADD $0x100,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| CMP %R13,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 402101 <main._omp_fn.6+0x171> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
