| Loop Id: 1337 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 1.08% |
|---|
| Loop Id: 1337 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 1.08% |
|---|
0x472a20 MOV -0x218(%RBP),%R13 [14] |
0x472a27 MOV -0x210(%RBP),%RAX [14] |
0x472a2e VMOVSD (%RAX,%R13,8),%XMM0 [10] |
0x472a34 VADDSD %XMM0,%XMM0,%XMM0 |
0x472a38 VDIVSD (%RDX,%R10,1),%XMM0,%XMM0 [9] |
0x472a3e VMOVSD (%R14,%R13,8),%XMM1 [8] |
0x472a44 VMOVHPD (%R8,%R13,8),%XMM1,%XMM1 [11] |
0x472a4a VADDPD %XMM1,%XMM1,%XMM1 |
0x472a4e MOV -0x238(%RBP),%R13 [14] |
0x472a55 VMOVSD (%R12,%R13,8),%XMM2 [12] |
0x472a5b MOV -0x220(%RBP),%R13 [14] |
0x472a62 VMOVHPD (%RBX,%R13,8),%XMM2,%XMM2 [7] |
0x472a68 VDIVPD %XMM2,%XMM1,%XMM1 |
0x472a6c MOV -0x78(%RBP),%RAX [14] |
0x472a70 VMOVSD (%RAX,%R10,1),%XMM2 [15] |
0x472a76 VMOVHPD (%R15,%R10,1),%XMM2,%XMM2 [13] |
0x472a7c VMULPD %XMM1,%XMM2,%XMM2 |
0x472a80 VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 |
0x472a85 MOV %RBX,%R13 |
0x472a88 MOV %RAX,%RBX |
0x472a8b MOV %R8,%R15 |
0x472a8e MOV %R12,%R8 |
0x472a91 MOV %R14,%R12 |
0x472a94 MOV -0x38(%RBP),%RDX [14] |
0x472a98 VADDSD (%RDX,%R11,1),%XMM2,%XMM2 [3] |
0x472a9e MOV -0x230(%RBP),%RAX [14] |
0x472aa5 VFMADD231SD (%RDI,%RAX,8),%XMM0,%XMM3 [6] |
0x472aab VADDSD %XMM2,%XMM3,%XMM2 |
0x472aaf VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 |
0x472ab4 VADDSD %XMM0,%XMM1,%XMM0 |
0x472ab8 MOV -0x30(%RBP),%RDX [14] |
0x472abc VADDSD (%RDX,%R11,1),%XMM3,%XMM1 [5] |
0x472ac2 VADDSD %XMM0,%XMM1,%XMM0 |
0x472ac6 VDIVSD %XMM0,%XMM2,%XMM0 |
0x472aca MOV -0x40(%RBP),%RDX [14] |
0x472ace VMOVSD %XMM0,(%RDX,%R11,1) [1] |
0x472ad4 MOV %RSI,%R9 |
0x472ad7 MOV %R8,%R12 |
0x472ada MOV %R15,%R8 |
0x472add MOV %RBX,%RSI |
0x472ae0 MOV %R13,%RBX |
0x472ae3 MOV -0x228(%RBP),%R15 [14] |
0x472aea MOV -0x150(%RBP),%RDX [14] |
0x472af1 MOV -0x208(%RBP),%R13 [14] |
0x472af8 VADDSD %XMM0,%XMM0,%XMM0 |
0x472afc VSUBSD (%RDI,%RAX,8),%XMM0,%XMM1 [6] |
0x472b01 VMOVSD %XMM1,(%RDI,%RAX,8) [6] |
0x472b06 VSUBSD (%RSI,%R10,1),%XMM0,%XMM1 [4] |
0x472b0c VMOVSD %XMM1,(%RSI,%R10,1) [4] |
0x472b12 VSUBSD (%R15,%R10,1),%XMM0,%XMM0 [2] |
0x472b18 VMOVSD %XMM0,(%R15,%R10,1) [2] |
0x472b1e ADD %R13,%R10 |
0x472b21 MOV %R9,%RSI |
0x472b24 ADD %R9,%R11 |
0x472b27 DEC %RCX |
0x472b2a JNE 472a20 |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105 |
-------------------------------------------------------------------------------- |
87: double xcos_dxi = 2.0 * xcos(d) / dx(i); |
88: double ycos_dyj = 2.0 * ycos(d) / dy(j); |
89: double zcos_dzk = 2.0 * zcos(d) / dz(k); |
[...] |
96: + psi_fr(d, g, i, k) * ycos_dyj |
97: + psi_bo(d, g, i, j) * zcos_dzk) |
98: / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z)); |
99: |
100: psi(d, g, z) = psi_d_g_z; |
101: |
102: /* Apply diamond-difference relationships */ |
103: psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k); |
104: psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k); |
105: psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j); |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.50 |
| CQA speedup if fully vectorized | 1.50 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P0, |
| Function | _ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted |
| Source | SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:96-105,forall.hpp:59-59,Operators.hpp:307-307 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 10.83 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 8.50 |
| P1 cycles | 8.67 |
| P2 cycles | 8.67 |
| P3 cycles | 2.00 |
| P4 cycles | 8.50 |
| P5 cycles | 1.60 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 1.40 |
| P10 cycles | 8.67 |
| P11 cycles | 12.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | 12.63 - 13.19 |
| Stall cycles (UFS) | 1.01 - 1.57 |
| Nb insns | 56.00 |
| Nb uops | 55.00 |
| Nb loads | 26.00 |
| Nb stores | 4.00 |
| Nb stack references | 12.00 |
| FLOP/cycle | 1.67 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 208.00 |
| Bytes stored | 32.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 5.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 16.67 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 9.09 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 33.33 |
| Vectorization ratio other | 66.67 |
| Vector-efficiency ratio all | 14.58 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | 13.64 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 16.67 |
| Vector-efficiency ratio other | 20.83 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.50 |
| CQA speedup if fully vectorized | 1.50 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.11 |
| Bottlenecks | P0, |
| Function | _ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted |
| Source | SweepSubdomain.cpp:87-89,SweepSubdomain.cpp:96-105,forall.hpp:59-59,Operators.hpp:307-307 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 12.00 |
| CQA cycles if no scalar integer | 12.00 |
| CQA cycles if FP arith vectorized | 8.00 |
| CQA cycles if fully vectorized | 8.00 |
| Front-end cycles | 10.83 |
| DIV/SQRT cycles | 4.00 |
| P0 cycles | 8.50 |
| P1 cycles | 8.67 |
| P2 cycles | 8.67 |
| P3 cycles | 2.00 |
| P4 cycles | 8.50 |
| P5 cycles | 1.60 |
| P6 cycles | 2.00 |
| P7 cycles | 2.00 |
| P8 cycles | 2.00 |
| P9 cycles | 1.40 |
| P10 cycles | 8.67 |
| P11 cycles | 12.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | 12.63 - 13.19 |
| Stall cycles (UFS) | 1.01 - 1.57 |
| Nb insns | 56.00 |
| Nb uops | 55.00 |
| Nb loads | 26.00 |
| Nb stores | 4.00 |
| Nb stack references | 12.00 |
| FLOP/cycle | 1.67 |
| Nb FLOP add-sub | 12.00 |
| Nb FLOP mul | 2.00 |
| Nb FLOP fma | 1.00 |
| Nb FLOP div | 4.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 20.00 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 208.00 |
| Bytes stored | 32.00 |
| Stride 0 | 1.00 |
| Stride 1 | 0.00 |
| Stride n | 0.00 |
| Stride unknown | 5.00 |
| Stride indirect | 6.00 |
| Vectorization ratio all | 16.67 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | 0.00 |
| Vectorization ratio mul | 100.00 |
| Vectorization ratio add_sub | 9.09 |
| Vectorization ratio fma | 0.00 |
| Vectorization ratio div_sqrt | 33.33 |
| Vectorization ratio other | 66.67 |
| Vector-efficiency ratio all | 14.58 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | 12.50 |
| Vector-efficiency ratio mul | 25.00 |
| Vector-efficiency ratio add_sub | 13.64 |
| Vector-efficiency ratio fma | 12.50 |
| Vector-efficiency ratio div_sqrt | 16.67 |
| Vector-efficiency ratio other | 20.83 |
| Path / |
| Function | _ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted |
| Source file and lines | forall.hpp:59-59 |
| Module | exec |
| nb instructions | 56 |
| nb uops | 55 |
| loop length | 272 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 12 |
| ADD-SUB / MUL ratio | 11.00 |
| micro-operation queue | 10.83 cycles |
| front end | 10.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 8.50 | 8.67 | 8.67 | 2.00 | 8.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 8.67 |
| cycles | 4.00 | 8.50 | 8.67 | 8.67 | 2.00 | 8.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 8.67 |
| Cycles executing div or sqrt instructions | 12.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| FE+BE cycles | 12.63-13.19 |
| Stall cycles | 1.01-1.57 |
| LB full (events) | 1.74-2.37 |
| Front-end | 10.83 |
| Dispatch | 8.67 |
| DIV/SQRT | 12.00 |
| Data deps. | 2.00 |
| Overall L1 | 12.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 17% |
| load | 0% |
| store | 0% |
| mul | 100% |
| add-sub | 9% |
| fma | 0% |
| div/sqrt | 33% |
| other | 100% |
| all | 16% |
| load | 0% |
| store | 0% |
| mul | 100% |
| add-sub | 9% |
| fma | 0% |
| div/sqrt | 33% |
| other | 66% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 25% |
| add-sub | 13% |
| fma | 12% |
| div/sqrt | 16% |
| other | 25% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 25% |
| add-sub | 13% |
| fma | 12% |
| div/sqrt | 16% |
| other | 20% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x218(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x210(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%RAX,%R13,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD (%RDX,%R10,1),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VMOVSD (%R14,%R13,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%R8,%R13,8),%XMM1,%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VADDPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| MOV -0x238(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R12,%R13,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x220(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%RBX,%R13,8),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VDIVPD %XMM2,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%RAX,%R10,1),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%R15,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VMULPD %XMM1,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOV %RBX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R12,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD (%RDX,%R11,1),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| MOV -0x230(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231SD (%RDI,%RAX,8),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM2,%XMM3,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD (%RDX,%R11,1),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD %XMM0,(%RDX,%R11,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R8,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R15,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R13,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x228(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x150(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x208(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBSD (%RDI,%RAX,8),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM1,(%RDI,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VSUBSD (%RSI,%R10,1),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM1,(%RSI,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VSUBSD (%R15,%R10,1),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM0,(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD %R13,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %R9,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| ADD %R9,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| JNE 472a20 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x770> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| Function | _ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted |
| Source file and lines | forall.hpp:59-59 |
| Module | exec |
| nb instructions | 56 |
| nb uops | 55 |
| loop length | 272 |
| used x86 registers | 15 |
| used mmx registers | 0 |
| used xmm registers | 4 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 12 |
| ADD-SUB / MUL ratio | 11.00 |
| micro-operation queue | 10.83 cycles |
| front end | 10.83 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 4.00 | 8.50 | 8.67 | 8.67 | 2.00 | 8.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 8.67 |
| cycles | 4.00 | 8.50 | 8.67 | 8.67 | 2.00 | 8.50 | 1.60 | 2.00 | 2.00 | 2.00 | 1.40 | 8.67 |
| Cycles executing div or sqrt instructions | 12.00 |
| Longest recurrence chain latency (RecMII) | 2.00 |
| FE+BE cycles | 12.63-13.19 |
| Stall cycles | 1.01-1.57 |
| LB full (events) | 1.74-2.37 |
| Front-end | 10.83 |
| Dispatch | 8.67 |
| DIV/SQRT | 12.00 |
| Data deps. | 2.00 |
| Overall L1 | 12.00 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 0% |
| all | 17% |
| load | 0% |
| store | 0% |
| mul | 100% |
| add-sub | 9% |
| fma | 0% |
| div/sqrt | 33% |
| other | 100% |
| all | 16% |
| load | 0% |
| store | 0% |
| mul | 100% |
| add-sub | 9% |
| fma | 0% |
| div/sqrt | 33% |
| other | 66% |
| all | 12% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | NA (no add-sub vectorizable/vectorized instructions) |
| fma | NA (no fma vectorizable/vectorized instructions) |
| other | 12% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 25% |
| add-sub | 13% |
| fma | 12% |
| div/sqrt | 16% |
| other | 25% |
| all | 14% |
| load | 12% |
| store | 12% |
| mul | 25% |
| add-sub | 13% |
| fma | 12% |
| div/sqrt | 16% |
| other | 20% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MOV -0x218(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x210(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%RAX,%R13,8),%XMM0 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD (%RDX,%R10,1),%XMM0,%XMM0 | 1 | 1 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 13-15 | 4 |
| VMOVSD (%R14,%R13,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%R8,%R13,8),%XMM1,%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VADDPD %XMM1,%XMM1,%XMM1 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| MOV -0x238(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%R12,%R13,8),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x220(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%RBX,%R13,8),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VDIVPD %XMM2,%XMM1,%XMM1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x78(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD (%RAX,%R10,1),%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVHPD (%R15,%R10,1),%XMM2,%XMM2 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4-12 | 1 |
| VMULPD %XMM1,%XMM2,%XMM2 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VSHUFPD $0x1,%XMM2,%XMM2,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| MOV %RBX,%R13 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RAX,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R8,%R15 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R12,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R14,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x38(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD (%RDX,%R11,1),%XMM2,%XMM2 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| MOV -0x230(%RBP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VFMADD231SD (%RDI,%RAX,8),%XMM0,%XMM3 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VADDSD %XMM2,%XMM3,%XMM2 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSHUFPD $0x1,%XMM1,%XMM1,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| MOV -0x30(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD (%RDX,%R11,1),%XMM3,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VADDSD %XMM0,%XMM1,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VDIVSD %XMM0,%XMM2,%XMM0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 13-15 | 4 |
| MOV -0x40(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD %XMM0,(%RDX,%R11,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| MOV %RSI,%R9 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R8,%R12 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R15,%R8 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %RBX,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV %R13,%RBX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| MOV -0x228(%RBP),%R15 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x150(%RBP),%RDX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| MOV -0x208(%RBP),%R13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM0,%XMM0,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VSUBSD (%RDI,%RAX,8),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM1,(%RDI,%RAX,8) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VSUBSD (%RSI,%R10,1),%XMM0,%XMM1 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM1,(%RSI,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| VSUBSD (%R15,%R10,1),%XMM0,%XMM0 | 1 | 0 | 0.50 | 0.33 | 0.33 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.33 | 3 | 0.50 |
| VMOVSD %XMM0,(%R15,%R10,1) | 1 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0.50 | 0.50 | 0.50 | 0 | 0 | 1 | 0.50 |
| ADD %R13,%R10 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| MOV %R9,%RSI | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| ADD %R9,%R11 | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| DEC %RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| JNE 472a20 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x770> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
