| Loop Id: 1978 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.47% |
|---|
| Loop Id: 1978 | Module: exec | Source: forall.hpp:59-59 [...] | Coverage: 0.47% |
|---|
0x4ab62d VMOVSD (%RSI,%RCX,8),%XMM9 [1] |
0x4ab632 VMOVSD 0x8(%RSI,%RCX,8),%XMM13 [1] |
0x4ab638 VMOVSD 0x10(%RSI,%RCX,8),%XMM1 [1] |
0x4ab63e VMOVSD 0x18(%RSI,%RCX,8),%XMM7 [1] |
0x4ab644 VMULSD (%RDI,%RCX,8),%XMM9,%XMM10 [2] |
0x4ab649 VMULSD 0x8(%RDI,%RCX,8),%XMM13,%XMM14 [2] |
0x4ab64f VMULSD 0x10(%RDI,%RCX,8),%XMM1,%XMM4 [2] |
0x4ab655 VMOVSD 0x30(%RSI,%RCX,8),%XMM1 [1] |
0x4ab65b VMULSD 0x18(%RDI,%RCX,8),%XMM7,%XMM8 [2] |
0x4ab661 VMULSD %XMM2,%XMM10,%XMM11 |
0x4ab665 VMOVSD 0x20(%RSI,%RCX,8),%XMM10 [1] |
0x4ab66b VMULSD %XMM2,%XMM14,%XMM15 |
0x4ab66f VMOVSD 0x28(%RSI,%RCX,8),%XMM14 [1] |
0x4ab675 VMULSD %XMM2,%XMM4,%XMM5 |
0x4ab679 VADDSD %XMM11,%XMM0,%XMM12 |
0x4ab67e VMULSD 0x20(%RDI,%RCX,8),%XMM10,%XMM11 [2] |
0x4ab684 VMULSD %XMM2,%XMM8,%XMM0 |
0x4ab688 VMOVSD 0x38(%RSI,%RCX,8),%XMM8 [1] |
0x4ab68e VADDSD %XMM15,%XMM12,%XMM3 |
0x4ab693 VMULSD 0x28(%RDI,%RCX,8),%XMM14,%XMM15 [2] |
0x4ab699 VMULSD %XMM2,%XMM11,%XMM12 |
0x4ab69d VADDSD %XMM5,%XMM3,%XMM6 |
0x4ab6a1 VMULSD 0x30(%RDI,%RCX,8),%XMM1,%XMM5 [2] |
0x4ab6a7 VMULSD %XMM2,%XMM15,%XMM3 |
0x4ab6ab VADDSD %XMM0,%XMM6,%XMM9 |
0x4ab6af VMULSD 0x38(%RDI,%RCX,8),%XMM8,%XMM0 [2] |
0x4ab6b5 ADD $0x8,%RCX |
0x4ab6b9 VMULSD %XMM2,%XMM5,%XMM6 |
0x4ab6bd VADDSD %XMM12,%XMM9,%XMM13 |
0x4ab6c2 VMULSD %XMM2,%XMM0,%XMM9 |
0x4ab6c6 VADDSD %XMM3,%XMM13,%XMM4 |
0x4ab6ca VADDSD %XMM6,%XMM4,%XMM7 |
0x4ab6ce VADDSD %XMM9,%XMM7,%XMM0 |
0x4ab6d3 CMP %RBX,%RCX |
0x4ab6d6 JNE 4ab62d |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59 |
-------------------------------------------------------------------------------- |
59: for (decltype(distance_it) i = 0; i < distance_it; ++i) { |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307 |
-------------------------------------------------------------------------------- |
307: return Ret{lhs} + rhs; |
/home/eoseret/qaas_runs_CPU_9468/171-112-3942/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58 |
-------------------------------------------------------------------------------- |
58: part_red += w(d) * psi(d,g,z) * volume(z); |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.35 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.00 |
| Bottlenecks | |
| Function | _ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0 |
| Source | forall.hpp:59-59,Operators.hpp:307-307,Population.cpp:58-58 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.00 |
| CQA cycles if no scalar integer | 24.00 |
| CQA cycles if FP arith vectorized | 10.20 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 7.00 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 12.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 0.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 24 |
| FE+BE cycles (UFS) | 24.19 |
| Stall cycles (UFS) | 16.46 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.00 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 2.35 |
| CQA speedup if fully vectorized | 8.00 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 2.00 |
| Bottlenecks | |
| Function | _ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0 |
| Source | forall.hpp:59-59,Operators.hpp:307-307,Population.cpp:58-58 |
| Source loop unroll info | not unrolled or unrolled with no peel/tail loop |
| Source loop unroll confidence level | max |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 24.00 |
| CQA cycles if no scalar integer | 24.00 |
| CQA cycles if FP arith vectorized | 10.20 |
| CQA cycles if fully vectorized | 3.00 |
| Front-end cycles | 7.00 |
| DIV/SQRT cycles | 8.00 |
| P0 cycles | 12.00 |
| P1 cycles | 5.33 |
| P2 cycles | 5.33 |
| P3 cycles | 0.00 |
| P4 cycles | 8.00 |
| P5 cycles | 1.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 0.00 |
| P10 cycles | 5.33 |
| P11 cycles | 0.00 |
| Inter-iter dependencies cycles | 24 |
| FE+BE cycles (UFS) | 24.19 |
| Stall cycles (UFS) | 16.46 |
| Nb insns | 35.00 |
| Nb uops | 34.00 |
| Nb loads | 16.00 |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 1.00 |
| Nb FLOP add-sub | 8.00 |
| Nb FLOP mul | 16.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 5.33 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 128.00 |
| Bytes stored | 0.00 |
| Stride 0 | 0.00 |
| Stride 1 | 2.00 |
| Stride n | 0.00 |
| Stride unknown | 0.00 |
| Stride indirect | 0.00 |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | 0.00 |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | NA |
| Vector-efficiency ratio all | 12.50 |
| Vector-efficiency ratio load | 12.50 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | 12.50 |
| Vector-efficiency ratio add_sub | 12.50 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | NA |
| Path / |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 175 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.50 |
| micro-operation queue | 7.00 cycles |
| front end | 7.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 8.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| cycles | 8.00 | 12.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 24.00 |
| FE+BE cycles | 24.19 |
| Stall cycles | 16.46 |
| PRF_FLOAT full (events) | 19.37 |
| Front-end | 7.00 |
| Dispatch | 12.00 |
| Data deps. | 24.00 |
| Overall L1 | 24.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RSI,%RCX,8),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x8(%RSI,%RCX,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x10(%RSI,%RCX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x18(%RSI,%RCX,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD (%RDI,%RCX,8),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD 0x8(%RDI,%RCX,8),%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD 0x10(%RDI,%RCX,8),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD 0x30(%RSI,%RCX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD 0x18(%RDI,%RCX,8),%XMM7,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x20(%RSI,%RCX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD %XMM2,%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x28(%RSI,%RCX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD %XMM2,%XMM4,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM11,%XMM0,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x20(%RDI,%RCX,8),%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM8,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x38(%RSI,%RCX,8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM15,%XMM12,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x28(%RDI,%RCX,8),%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM5,%XMM3,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x30(%RDI,%RCX,8),%XMM1,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM15,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM0,%XMM6,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x38(%RDI,%RCX,8),%XMM8,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0x8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULSD %XMM2,%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM9,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD %XMM2,%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM3,%XMM13,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM6,%XMM4,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM9,%XMM7,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 4ab62d <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x20d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
| nb instructions | 35 |
| nb uops | 34 |
| loop length | 175 |
| used x86 registers | 4 |
| used mmx registers | 0 |
| used xmm registers | 16 |
| used ymm registers | 0 |
| used zmm registers | 0 |
| nb stack references | 0 |
| ADD-SUB / MUL ratio | 0.50 |
| micro-operation queue | 7.00 cycles |
| front end | 7.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 8.00 | 8.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| cycles | 8.00 | 12.00 | 5.33 | 5.33 | 0.00 | 8.00 | 1.00 | 0.00 | 0.00 | 0.00 | 0.00 | 5.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 24.00 |
| FE+BE cycles | 24.19 |
| Stall cycles | 16.46 |
| PRF_FLOAT full (events) | 19.37 |
| Front-end | 7.00 |
| Dispatch | 12.00 |
| Data deps. | 24.00 |
| Overall L1 | 24.00 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 0% |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| all | 12% |
| load | 12% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | 12% |
| add-sub | 12% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | NA (no other vectorizable/vectorized instructions) |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| VMOVSD (%RSI,%RCX,8),%XMM9 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x8(%RSI,%RCX,8),%XMM13 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x10(%RSI,%RCX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMOVSD 0x18(%RSI,%RCX,8),%XMM7 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD (%RDI,%RCX,8),%XMM9,%XMM10 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD 0x8(%RDI,%RCX,8),%XMM13,%XMM14 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD 0x10(%RDI,%RCX,8),%XMM1,%XMM4 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMOVSD 0x30(%RSI,%RCX,8),%XMM1 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD 0x18(%RDI,%RCX,8),%XMM7,%XMM8 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x20(%RSI,%RCX,8),%XMM10 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD %XMM2,%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x28(%RSI,%RCX,8),%XMM14 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VMULSD %XMM2,%XMM4,%XMM5 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM11,%XMM0,%XMM12 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x20(%RDI,%RCX,8),%XMM10,%XMM11 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM8,%XMM0 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VMOVSD 0x38(%RSI,%RCX,8),%XMM8 | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
| VADDSD %XMM15,%XMM12,%XMM3 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x28(%RDI,%RCX,8),%XMM14,%XMM15 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM11,%XMM12 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM5,%XMM3,%XMM6 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x30(%RDI,%RCX,8),%XMM1,%XMM5 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| VMULSD %XMM2,%XMM15,%XMM3 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM0,%XMM6,%XMM9 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD 0x38(%RDI,%RCX,8),%XMM8,%XMM0 | 1 | 0.50 | 0.50 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 4 | 0.50 |
| ADD $0x8,%RCX | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.17 |
| VMULSD %XMM2,%XMM5,%XMM6 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM12,%XMM9,%XMM13 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VMULSD %XMM2,%XMM0,%XMM9 | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0.50 |
| VADDSD %XMM3,%XMM13,%XMM4 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM6,%XMM4,%XMM7 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| VADDSD %XMM9,%XMM7,%XMM0 | 1 | 0 | 0.50 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 3 | 0.50 |
| CMP %RBX,%RCX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 1 | 0.20 |
| JNE 4ab62d <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x20d> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
