OV - exec - Loop 2065

	Loop Id: 2065	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.46%

0x4bd07c VMOVUPD	(%RSI,%RAX,1),%YMM7    [1]

0x4bd081 VMULPD	(%R9,%RAX,1),%YMM7,%YMM9    [2]

0x4bd087 VMOVUPD	0x40(%RSI,%RAX,1),%YMM11    [1]

0x4bd08d VMULPD	0x40(%R9,%RAX,1),%YMM11,%YMM12    [2]

0x4bd094 VMOVUPD	0x80(%RSI,%RAX,1),%YMM15    [1]

0x4bd09d VMOVUPD	0x60(%RSI,%RAX,1),%YMM13    [1]

0x4bd0a3 VMOVUPD	0xa0(%RSI,%RAX,1),%YMM4    [1]

0x4bd0ac VMULPD	0x60(%R9,%RAX,1),%YMM13,%YMM14    [2]

0x4bd0b3 VMULPD	0x80(%R9,%RAX,1),%YMM15,%YMM3    [2]

0x4bd0bd VMOVUPD	0xc0(%RSI,%RAX,1),%YMM5    [1]

0x4bd0c6 VMULPD	0xa0(%R9,%RAX,1),%YMM4,%YMM6    [2]

0x4bd0d0 VFMADD132PD	%YMM8,%YMM0,%YMM9

0x4bd0d5 VMOVUPD	0x20(%RSI,%RAX,1),%YMM0    [1]

0x4bd0db VMULPD	0x20(%R9,%RAX,1),%YMM0,%YMM10    [2]

0x4bd0e2 VMULPD	0xc0(%R9,%RAX,1),%YMM5,%YMM7    [2]

0x4bd0ec VFMADD132PD	%YMM8,%YMM9,%YMM10

0x4bd0f1 VMOVUPD	0xe0(%RSI,%RAX,1),%YMM9    [1]

0x4bd0fa VMULPD	0xe0(%R9,%RAX,1),%YMM9,%YMM0    [2]

0x4bd104 ADD	$0x100,%RAX

0x4bd10a VFMADD132PD	%YMM8,%YMM10,%YMM12

0x4bd10f VFMADD132PD	%YMM8,%YMM12,%YMM14

0x4bd114 VFMADD132PD	%YMM8,%YMM14,%YMM3

0x4bd119 VFMADD132PD	%YMM8,%YMM3,%YMM6

0x4bd11e VFMADD132PD	%YMM8,%YMM6,%YMM7

0x4bd123 VFMADD132PD	%YMM8,%YMM7,%YMM0

0x4bd128 CMP	%RAX,%R14

0x4bd12b JNE	4bd07c

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.38
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:307-307,forall.hpp:59-59
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	23.11
CQA cycles if fully vectorized	16.00
Front-end cycles	5.67
DIV/SQRT cycles	8.00
P0 cycles	8.00
P1 cycles	5.33
P2 cycles	5.33
P3 cycles	0.00
P4 cycles	0.60
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.40
P10 cycles	5.33
P11 cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	32.14
Stall cycles (UFS)	25.79
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.38
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	4.00
Bottlenecks
Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source	Operators.hpp:307-307,forall.hpp:59-59
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	32.00
CQA cycles if no scalar integer	32.00
CQA cycles if FP arith vectorized	23.11
CQA cycles if fully vectorized	16.00
Front-end cycles	5.67
DIV/SQRT cycles	8.00
P0 cycles	8.00
P1 cycles	5.33
P2 cycles	5.33
P3 cycles	0.00
P4 cycles	0.60
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.40
P10 cycles	5.33
P11 cycles	0.00
Inter-iter dependencies cycles	32
FE+BE cycles (UFS)	32.14
Stall cycles (UFS)	25.79
Nb insns	27.00
Nb uops	26.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	512.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 32.00 to 16.00 cycles (2.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Recompile with march=sapphirerapids. CQA target is Sapphire_Rapids_8f (Intel(R) Xeon(R) Sapphire Rapids) but specialization flags are -march=haswell
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 32 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

16 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
64: multiply (32 inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	27
nb uops	26
loop length	181
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	14
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	8.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33
cycles	8.00	8.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	32.14
Stall cycles	25.79
LB full (events)	27.42

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4bd07c

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput
VMOVUPD (%RSI,%RAX,1),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD (%R9,%RAX,1),%YMM7,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0x40(%RSI,%RAX,1),%YMM11	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x40(%R9,%RAX,1),%YMM11,%YMM12	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0x80(%RSI,%RAX,1),%YMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMOVUPD 0x60(%RSI,%RAX,1),%YMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMOVUPD 0xa0(%RSI,%RAX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x60(%R9,%RAX,1),%YMM13,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMULPD 0x80(%R9,%RAX,1),%YMM15,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0xc0(%RSI,%RAX,1),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0xa0(%R9,%RAX,1),%YMM4,%YMM6	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VFMADD132PD %YMM8,%YMM0,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VMOVUPD 0x20(%RSI,%RAX,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x20(%R9,%RAX,1),%YMM0,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMULPD 0xc0(%R9,%RAX,1),%YMM5,%YMM7	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VFMADD132PD %YMM8,%YMM9,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VMOVUPD 0xe0(%RSI,%RAX,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0xe0(%R9,%RAX,1),%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
VFMADD132PD %YMM8,%YMM10,%YMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM12,%YMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM14,%YMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM3,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM6,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM7,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50
CMP %RAX,%R14	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
JNE 4bd07c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x25c>	1	0.50	0	0	0	0	0.50	0	0	0	0.50

Function	void RAJA::internal::StatementExecutor, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >::exec, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&>(RAJA::internal::LoopData, RAJA::statement::For<2l, RAJA::policy::loop::loop_exec, RAJA::statement::Lambda<0l> > > >, camp::tuple, Kripke::Direction>, RAJA::impl::Span, Kripke::Group>, RAJA::impl::Span, Kripke::Zone> >, camp::tuple<>, PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, double) const::{lambda(Kripke::Direction, Kripke::Group, Kripke::Zone)#1}>&) [clone ._omp_fn.0]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 32.00 to 16.00 cycles (2.00x speedup).

Details

Workaround

Recompile with march=sapphirerapids. CQA target is Sapphire_Rapids_8f (Intel(R) Xeon(R) Sapphire Rapids) but specialization flags are -march=haswell
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 32 FMA (fused multiply-add) operations.

Vector unaligned load/store instructions

Detected 8 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 8 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

16 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 96 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
64: multiply (32 inside FMA instructions)

The binary loop is loading 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	27
nb uops	26
loop length	181
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	14
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.00	8.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33
cycles	8.00	8.00	5.33	5.33	0.00	0.60	1.00	0.00	0.00	0.00	0.40	5.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	32.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	32.14
Stall cycles	25.79
LB full (events)	27.42

Cycles summary

Front-end	5.67
Dispatch	8.00
Data deps.	32.00
Overall L1	32.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 32.00 cycles. At this rate:

8% of peak load performance is reached (16.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4bd07c

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput
VMOVUPD (%RSI,%RAX,1),%YMM7	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD (%R9,%RAX,1),%YMM7,%YMM9	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0x40(%RSI,%RAX,1),%YMM11	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x40(%R9,%RAX,1),%YMM11,%YMM12	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0x80(%RSI,%RAX,1),%YMM15	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMOVUPD 0x60(%RSI,%RAX,1),%YMM13	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMOVUPD 0xa0(%RSI,%RAX,1),%YMM4	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x60(%R9,%RAX,1),%YMM13,%YMM14	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMULPD 0x80(%R9,%RAX,1),%YMM15,%YMM3	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMOVUPD 0xc0(%RSI,%RAX,1),%YMM5	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0xa0(%R9,%RAX,1),%YMM4,%YMM6	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VFMADD132PD %YMM8,%YMM0,%YMM9	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VMOVUPD 0x20(%RSI,%RAX,1),%YMM0	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0x20(%R9,%RAX,1),%YMM0,%YMM10	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VMULPD 0xc0(%R9,%RAX,1),%YMM5,%YMM7	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
VFMADD132PD %YMM8,%YMM9,%YMM10	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VMOVUPD 0xe0(%RSI,%RAX,1),%YMM9	1	0	0	0.33	0.33	0	0	0	0.33	0-1	0.33
VMULPD 0xe0(%R9,%RAX,1),%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0.33	4	0.50
ADD $0x100,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
VFMADD132PD %YMM8,%YMM10,%YMM12	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM12,%YMM14	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM14,%YMM3	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM3,%YMM6	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM6,%YMM7	1	0.50	0.50	0	0	0	0	0	0	4	0.50
VFMADD132PD %YMM8,%YMM7,%YMM0	1	0.50	0.50	0	0	0	0	0	0	4	0.50
CMP %RAX,%R14	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
JNE 4bd07c <_ZN4RAJA8internal17StatementExecutorINS_9statement8CollapseINS_26omp_parallel_collapse_execEN4camp7int_seqIlJLl0ELl1EEEEJNS2_3ForILl2ENS_6policy4loop9loop_execEJNS2_6LambdaILl0EJEEEEEEEEEE4execIRNS0_8LoopDataINS5_4listIJSF_EEENS5_5tupleIJNS_4impl4SpanINS_9Iterators16numeric_iteratorIN6Kripke9DirectionElPSR_EESR_EENSN_INSP_INSQ_5GroupElPSV_EESV_EENSN_INSP_INSQ_4ZoneElPSZ_EESZ_EEEEENSL_IJEEEJZNK14PopulationSdomclINSQ_11ArchLayoutTINSQ_12ArchT_OpenMPENSQ_11LayoutT_DGZEEEEEvT_NSQ_6SdomIdERKNSQ_4Core3SetES1G_S1G_RNS1D_5FieldIdJSR_SV_SZ_EEERNS1H_IdJSR_EEERNS1H_IdJSZ_EEEPdEUlSR_SV_SZ_E_EEEEEvOS1B_._omp_fn.0+0x25c>	1	0.50	0	0	0	0	0.50	0	0	0	0.50

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code