OV - exec - Function __intel_rtdd

	Function: __intel_rtdd_indep	Module: exec	Source: :0-0	Coverage: 0.01%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x40dad0 ENDBR64

0x40dad4 PUSH	%R15

0x40dad6 PUSH	%R14

0x40dad8 PUSH	%RBX

0x40dad9 MOV	%RSI,%R14

0x40dadc MOV	%RDI,%R15

0x40dadf DEC	%R14D

0x40dae2 XOR	%EBX,%EBX

0x40dae4 XOR	%ESI,%ESI

0x40dae6 MOV	%R14D,%EDX

0x40dae9 CALL	40db30 <quicksort>

0x40daee TEST	%R14D,%R14D

0x40daf1 CMOVLE	%EBX,%R14D

0x40daf5 SAL	$0x4,%R14

0x40daf9 ADD	$0x10,%R14

0x40dafd XOR	%EAX,%EAX

(37) 0x40daff LEA	0x10(%RAX),%RCX

(37) 0x40db03 CMP	%RCX,%R14

(37) 0x40db06 JE	40db1c

(37) 0x40db08 MOV	0x8(%R15,%RAX,1),%RDX

(37) 0x40db0d CMP	0x10(%R15,%RAX,1),%RDX

(37) 0x40db12 MOV	%RCX,%RAX

(37) 0x40db15 JB	40daff

0x40db17 MOV	$0x1,%EBX

0x40db1c MOV	%RBX,%RAX

0x40db1f POP	%RBX

0x40db20 POP	%R14

0x40db22 POP	%R15

0x40db24 RET

0x40db25 NOPW	%CS:(%RAX,%RAX,1)

0x40db2f NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.00 to 0.25 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

quicksort: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	72
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	1.33	1.33	2.00	1.00	1.50	2.00	2.00	2.00	1.00	1.33
cycles	1.50	1.00	1.33	1.33	2.00	1.00	1.50	2.00	2.00	2.00	1.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.93-3.94
Stall cycles	0.00

Cycles summary

Front-end	4.00
Dispatch	2.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 2.00 cycles (2.00x speedup).

ASM code

In the binary file, the address of the function is: 40dad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ENDBR64
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
DEC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 40db30 <quicksort>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
CMOVLE %EBX,%R14D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
SAL $0x4,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD $0x10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

quicksort: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	24
nb uops	24
loop length	72
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	1.33	1.33	2.00	1.00	1.50	2.00	2.00	2.00	1.00	1.33
cycles	1.50	1.00	1.33	1.33	2.00	1.00	1.50	2.00	2.00	2.00	1.00	1.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.93-3.94
Stall cycles	0.00

Cycles summary

Front-end	4.00
Dispatch	2.00
Overall L1	4.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	7%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 40dad0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ENDBR64
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %RSI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
DEC %R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 40db30 <quicksort>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
TEST %R14D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
CMOVLE %EBX,%R14D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
SAL $0x4,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD $0x10,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x1,%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Name	Coverage (%)	Time (s)
▼__intel_rtdd_indep–	0.01	0
○Loop 37 - - exec	0	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code