OV - exec - Function quicksort

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x40db30 CMP	%EDX,%ESI

0x40db32 JGE	40dbd6

0x40db38 PUSH	%R15

0x40db3a PUSH	%R14

0x40db3c PUSH	%R13

0x40db3e PUSH	%R12

0x40db40 PUSH	%RBX

0x40db41 MOV	%EDX,%EBX

0x40db43 MOV	%RDI,%R14

0x40db46 MOVSXD	%EDX,%R15

0x40db49 MOV	%R15,%R12

0x40db4c SAL	$0x4,%R12

0x40db50 ADD	%RDI,%R12

(39) 0x40db53 MOVSXD	%ESI,%RAX

(39) 0x40db56 MOV	%R15,%RCX

(39) 0x40db59 SUB	%RAX,%RCX

(39) 0x40db5c SAL	$0x4,%RAX

(39) 0x40db60 ADD	%R14,%RAX

(39) 0x40db63 MOV	%ESI,%EDX

  (38) 0x40db65 MOV	(%RAX),%RDI

  (38) 0x40db68 CMP	(%R12),%RDI

  (38) 0x40db6c JAE	40db8f

  (38) 0x40db6e MOVSXD	%EDX,%RDX

  (38) 0x40db71 MOV	%RDX,%R8

  (38) 0x40db74 SAL	$0x4,%R8

  (38) 0x40db78 MOV	0x8(%RAX),%R9

  (38) 0x40db7c MOVUPS	(%R14,%R8,1),%XMM0

  (38) 0x40db81 MOVUPS	%XMM0,(%RAX)

  (38) 0x40db84 MOV	%RDI,(%R14,%R8,1)

  (38) 0x40db88 MOV	%R9,0x8(%R14,%R8,1)

  (38) 0x40db8d INC	%EDX

  (38) 0x40db8f ADD	$0x10,%RAX

  (38) 0x40db93 DEC	%RCX

  (38) 0x40db96 JNE	40db65

(39) 0x40db98 MOVSXD	%EDX,%R13

(39) 0x40db9b MOV	%R13,%RAX

(39) 0x40db9e SAL	$0x4,%RAX

(39) 0x40dba2 MOVUPS	(%R12),%XMM0

(39) 0x40dba7 MOVUPS	(%R14,%RAX,1),%XMM1

(39) 0x40dbac MOVUPS	%XMM1,(%R12)

(39) 0x40dbb1 MOVUPS	%XMM0,(%R14,%RAX,1)

(39) 0x40dbb6 LEA	-0x1(%R13),%EDX

(39) 0x40dbba MOV	%R14,%RDI

(39) 0x40dbbd CALL	40db30 <quicksort>

(39) 0x40dbc2 INC	%R13D

(39) 0x40dbc5 MOV	%R13D,%ESI

(39) 0x40dbc8 CMP	%EBX,%R13D

(39) 0x40dbcb JL	40db53

0x40dbcd POP	%RBX

0x40dbce POP	%R12

0x40dbd0 POP	%R13

0x40dbd2 POP	%R14

0x40dbd4 POP	%R15

0x40dbd6 RET

0x40dbd7 NOP

0x40dbd8 NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.22 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	21
nb uops	21
loop length	54
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.13	2.00	2.00	2.50	0.93	1.50	2.50	2.50	2.50	0.93	2.00
cycles	1.50	1.13	2.00	2.00	2.50	0.93	1.50	2.50	2.50	2.50	0.93	2.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.60-3.61
Stall cycles	0.00

Cycles summary

Front-end	3.50
Dispatch	2.50
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.50 cycles (1.40x speedup).

ASM code

In the binary file, the address of the function is: 40db30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JGE 40dbd6 <quicksort+0xa6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVSXD %EDX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD %RDI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Source file and lines
Module	exec

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 0.22 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	21
nb uops	21
loop length	54
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.50 cycles
front end	3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.13	2.00	2.00	2.50	0.93	1.50	2.50	2.50	2.50	0.93	2.00
cycles	1.50	1.13	2.00	2.00	2.50	0.93	1.50	2.50	2.50	2.50	0.93	2.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

NA

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.60-3.61
Stall cycles	0.00

Cycles summary

Front-end	3.50
Dispatch	2.50
Overall L1	3.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.50 to 2.50 cycles (1.40x speedup).

ASM code

In the binary file, the address of the function is: 40db30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JGE 40dbd6 <quicksort+0xa6>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVSXD %EDX,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R15,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SAL $0x4,%R12	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD %RDI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Name	Coverage (%)	Time (s)
▼quicksort–	0.09	0.05
▼Loop 39 - - exec–	0.01	0.01
○Loop 38 - - exec	0.07	0.04

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code