OV - exec - Loop 39

	Loop Id: 39	Module: exec	Source: :0-0	Coverage: 0.01%

0x40db53 MOVSXD	%ESI,%RAX

0x40db56 MOV	%R15,%RCX

0x40db59 SUB	%RAX,%RCX

0x40db5c SAL	$0x4,%RAX

0x40db60 ADD	%R14,%RAX

0x40db63 MOV	%ESI,%EDX

  (38) 0x40db65 MOV	(%RAX),%RDI

  (38) 0x40db68 CMP	(%R12),%RDI

  (38) 0x40db6c JAE	40db8f

  (38) 0x40db6e MOVSXD	%EDX,%RDX

  (38) 0x40db71 MOV	%RDX,%R8

  (38) 0x40db74 SAL	$0x4,%R8

  (38) 0x40db78 MOV	0x8(%RAX),%R9

  (38) 0x40db7c MOVUPS	(%R14,%R8,1),%XMM0

  (38) 0x40db81 MOVUPS	%XMM0,(%RAX)

  (38) 0x40db84 MOV	%RDI,(%R14,%R8,1)

  (38) 0x40db88 MOV	%R9,0x8(%R14,%R8,1)

  (38) 0x40db8d INC	%EDX

  (38) 0x40db8f ADD	$0x10,%RAX

  (38) 0x40db93 DEC	%RCX

  (38) 0x40db96 JNE	40db65

0x40db98 MOVSXD	%EDX,%R13

0x40db9b MOV	%R13,%RAX

0x40db9e SAL	$0x4,%RAX

0x40dba2 MOVUPS	(%R12),%XMM0

0x40dba7 MOVUPS	(%R14,%RAX,1),%XMM1

0x40dbac MOVUPS	%XMM1,(%R12)

0x40dbb1 MOVUPS	%XMM0,(%R14,%RAX,1)

0x40dbb6 LEA	-0x1(%R13),%EDX

0x40dbba MOV	%R14,%RDI

0x40dbbd CALL	40db30 <quicksort>

0x40dbc2 INC	%R13D

0x40dbc5 MOV	%R13D,%ESI

0x40dbc8 CMP	%EBX,%R13D

0x40dbcb JL	40db53

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks
Function	quicksort
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.62
Front-end cycles	3.33
DIV/SQRT cycles	1.70
P0 cycles	1.87
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.50
P4 cycles	1.87
P5 cycles	1.70
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.87
P10 cycles	0.67
P11 cycles	0.00
Inter-iter dependencies cycles	6
FE+BE cycles (UFS)	3.30 - 3.31
Stall cycles (UFS)	0.00
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	44.44
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	9.70
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks
Function	quicksort
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	0.62
Front-end cycles	3.33
DIV/SQRT cycles	1.70
P0 cycles	1.87
P1 cycles	0.67
P2 cycles	0.67
P3 cycles	1.50
P4 cycles	1.87
P5 cycles	1.70
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.87
P10 cycles	0.67
P11 cycles	0.00
Inter-iter dependencies cycles	6
FE+BE cycles (UFS)	3.30 - 3.31
Stall cycles (UFS)	0.00
Nb insns	20.00
Nb uops	20.00
Nb loads	2.00
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	10.67
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	44.44
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	16.67
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	quicksort
Source file and lines
Module	exec

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.00 to 0.62 cycles (9.70x speedup).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

quicksort: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	20
nb uops	20
loop length	71
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.87	0.67	0.67	1.50	1.87	1.70	1.50	1.50	1.50	1.87	0.67
cycles	1.70	1.87	0.67	0.67	1.50	1.87	1.70	1.50	1.50	1.50	1.87	0.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	6.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.30-3.31
Stall cycles	0.00

Cycles summary

Front-end	3.33
Dispatch	1.87
Data deps.	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40db53

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVSXD %ESI,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVSXD %EDX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
MOVUPS (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
MOVUPS (%R14,%RAX,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
MOVUPS %XMM1,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
MOVUPS %XMM0,(%R14,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
LEA -0x1(%R13),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 40db30 <quicksort>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP %EBX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JL 40db53 <quicksort+0x23>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Function	quicksort
Source file and lines
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

quicksort: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 4 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 4 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please look into your compiler manual for march=native or equivalent
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes. The binary loop is storing 32 bytes.

General properties

nb instructions	20
nb uops	20
loop length	71
used x86 registers	10
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.70	1.87	0.67	0.67	1.50	1.87	1.70	1.50	1.50	1.50	1.87	0.67
cycles	1.70	1.87	0.67	0.67	1.50	1.87	1.70	1.50	1.50	1.50	1.87	0.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	6.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.30-3.31
Stall cycles	0.00

Cycles summary

Front-end	3.33
Dispatch	1.87
Data deps.	6.00
Overall L1	6.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	44%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	16%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 40db53

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOVSXD %ESI,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R15,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SUB %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
ADD %R14,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVSXD %EDX,%R13	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33
MOV %R13,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SAL $0x4,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50
MOVUPS (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
MOVUPS (%R14,%RAX,1),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
MOVUPS %XMM1,(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
MOVUPS %XMM0,(%R14,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
LEA -0x1(%R13),%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 40db30 <quicksort>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
INC %R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP %EBX,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JL 40db53 <quicksort+0x23>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code