OV - exec - Loop 1099 - libkripke.so

	Loop Id: 1099	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 0.07%

0x641a0 MOV	-0x48(%RBP),%RAX

0x641a4 CMP	-0x40(%RBP),%RAX

0x641a8 LEA	0x1(%RAX),%RAX

0x641ac MOV	%RAX,-0x48(%RBP)

0x641b0 JE	640d0

0x641b6 CMPQ	$0,-0x38(%RBP)

0x641bb JLE	641a0

0x641bd MOV	-0x108(%RBP),%RAX

0x641c4 MOV	-0x118(%RBP),%RCX

0x641cb MOV	(%RAX,%RCX,8),%RCX

0x641cf IMUL	-0x100(%RBP),%RCX

0x641d7 ADD	-0x30(%RBP),%RCX

0x641db ADD	-0x110(%RBP),%RCX

0x641e2 MOV	-0xf8(%RBP),%RAX

0x641e9 LEA	(%RCX,%RAX,1),%R11

0x641ed MOV	-0x48(%RBP),%RSI

0x641f1 ADD	%RSI,%R11

0x641f4 ADD	%RSI,%RAX

0x641f7 ADD	%RAX,%RCX

0x641fa MOV	-0x68(%RBP),%RAX

0x641fe IMUL	%RSI,%RAX

0x64202 MOV	%RAX,-0x160(%RBP)

0x64209 XOR	%ESI,%ESI

0x6420b JMP	64257

  (1100) 0x64210 VXORPD	%XMM0,%XMM0,%XMM0

  (1100) 0x64214 MOV	-0x160(%RBP),%RAX

  (1100) 0x6421b MOV	-0x50(%RBP),%RSI

  (1100) 0x6421f ADD	%RSI,%RAX

  (1100) 0x64222 ADD	-0x150(%RBP),%RAX

  (1100) 0x64229 VMOVSD	(%R12,%RAX,8),%XMM1

  (1100) 0x6422f MOV	-0x158(%RBP),%RDX

  (1100) 0x64236 LEA	(%RDX,%RSI,1),%RAX

  (1100) 0x6423a VFMADD213SD	(%R10,%RAX,8),%XMM0,%XMM1

  (1100) 0x64240 VMOVSD	%XMM1,(%R10,%RAX,8)

  (1100) 0x64246 CMP	-0x148(%RBP),%RSI

  (1100) 0x6424d LEA	0x1(%RSI),%RSI

  (1100) 0x64251 JE	641a0

  (1100) 0x64257 MOV	%RSI,-0x50(%RBP)

  (1100) 0x6425b LEA	(%R14,%RSI,1),%RDX

  (1100) 0x6425f MOVSXD	(%R13,%RDX,4),%RSI

  (1100) 0x64264 TEST	%RSI,%RSI

  (1100) 0x64267 JLE	64210

  (1100) 0x64269 MOV	-0x130(%RBP),%RAX

  (1100) 0x64270 MOV	(%RAX,%RDX,8),%RAX

  (1100) 0x64274 ADD	%RAX,%RSI

  (1100) 0x64277 LEA	0x1(%RAX),%RDX

  (1100) 0x6427b CMP	%RDX,%RSI

  (1100) 0x6427e CMOVLE	%RDX,%RSI

  (1100) 0x64282 MOV	%RSI,%RDX

  (1100) 0x64285 SUB	%RAX,%RDX

  (1100) 0x64288 MOV	%RDX,%R8

  (1100) 0x6428b AND	$-0x4,%R8

  (1100) 0x6428f JE	64370

  (1100) 0x64295 MOV	%RDX,-0x138(%RBP)

  (1100) 0x6429c LEA	-0x1(%R8),%RDX

  (1100) 0x642a0 LEA	(%R9,%RAX,8),%R13

  (1100) 0x642a4 MOV	%RAX,-0x140(%RBP)

  (1100) 0x642ab LEA	(%RDI,%RAX,8),%RDI

  (1100) 0x642af VXORPD	%XMM0,%XMM0,%XMM0

  (1100) 0x642b3 XOR	%R10D,%R10D

  (1100) 0x642b6 NOPW	%CS:(%RAX,%RAX,1)

    (1102) 0x642c0 MOV	(%RDI,%R10,8),%R9

    (1102) 0x642c4 IMUL	%RBX,%R9

    (1102) 0x642c8 ADD	%RCX,%R9

    (1102) 0x642cb MOV	0x8(%RDI,%R10,8),%R14

    (1102) 0x642d0 IMUL	%RBX,%R14

    (1102) 0x642d4 ADD	%RCX,%R14

    (1102) 0x642d7 MOV	0x10(%RDI,%R10,8),%R12

    (1102) 0x642dc IMUL	%RBX,%R12

    (1102) 0x642e0 ADD	%RCX,%R12

    (1102) 0x642e3 MOV	0x18(%RDI,%R10,8),%RAX

    (1102) 0x642e8 IMUL	%RBX,%RAX

    (1102) 0x642ec ADD	%RCX,%RAX

    (1102) 0x642ef VMOVSD	(%R15,%R12,8),%XMM1

    (1102) 0x642f5 VMOVHPD	(%R15,%RAX,8),%XMM1,%XMM1

    (1102) 0x642fb VMOVSD	(%R15,%R9,8),%XMM2

    (1102) 0x64301 VMOVHPD	(%R15,%R14,8),%XMM2,%XMM2

    (1102) 0x64307 VINSERTF128	$0x1,%XMM1,%YMM2,%YMM1

    (1102) 0x6430d VFMADD231PD	(%R13,%R10,8),%YMM1,%YMM0

    (1102) 0x64314 ADD	$0x4,%R10

    (1102) 0x64318 CMP	%RDX,%R10

    (1102) 0x6431b JBE	642c0

  (1100) 0x6431d VEXTRACTF128	$0x1,%YMM0,%XMM1

  (1100) 0x64323 VADDPD	%XMM1,%XMM0,%XMM0

  (1100) 0x64327 VSHUFPD	$0x1,%XMM0,%XMM0,%XMM1

  (1100) 0x6432c VADDSD	%XMM1,%XMM0,%XMM0

  (1100) 0x64330 CMP	%R8,-0x138(%RBP)

  (1100) 0x64337 MOV	-0x128(%RBP),%R14

  (1100) 0x6433e MOV	-0x120(%RBP),%R13

  (1100) 0x64345 MOV	-0x88(%RBP),%RDI

  (1100) 0x6434c MOV	-0x80(%RBP),%R9

  (1100) 0x64350 MOV	-0x78(%RBP),%R10

  (1100) 0x64354 MOV	-0x70(%RBP),%R12

  (1100) 0x64358 MOV	-0x140(%RBP),%RAX

  (1100) 0x6435f JE	64214

  (1100) 0x64365 JMP	64377

  (1100) 0x64370 VXORPD	%XMM0,%XMM0,%XMM0

  (1100) 0x64374 XOR	%R8D,%R8D

  (1100) 0x64377 ADD	%RAX,%R8

  (1100) 0x6437a NOPW	(%RAX,%RAX,1)

    (1101) 0x64380 MOV	(%RDI,%R8,8),%RAX

    (1101) 0x64384 IMUL	%RBX,%RAX

    (1101) 0x64388 ADD	%R11,%RAX

    (1101) 0x6438b VMOVSD	(%R15,%RAX,8),%XMM1

    (1101) 0x64391 VFMADD231SD	(%R9,%R8,8),%XMM1,%XMM0

    (1101) 0x64397 INC	%R8

    (1101) 0x6439a CMP	%R8,%RSI

    (1101) 0x6439d JNE	64380

  (1100) 0x6439f JMP	64214

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 105 - 217

--------------------------------------------------------------------------------

105:     return TYPE(value + a);

[...]

217:     return (value < x.value);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97

--------------------------------------------------------------------------------

87:             MixElem mix_start = zone_to_mixelem(z);

88:             MixElem mix_stop = mix_start + zone_to_num_mixelem(z);

89:

90:             double sigs_z = 0.0;

91:             for(MixElem mix = mix_start;mix < mix_stop;++ mix){

92:               Material mat = mixelem_to_material(mix);

93:               double fraction = mixelem_to_fraction(mix);

94:

95:               sigs_z += sigs(mat, n, global_g, global_gp) * fraction;

96:             }

97:             phi_out(nm, g, z) += sigs_z * phi(nm, gp, z);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 81

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue, P2, P3, P11,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.31
Front-end cycles	4.00
DIV/SQRT cycles	2.20
P0 cycles	3.40
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	1.00
P4 cycles	2.20
P5 cycles	2.20
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.20
P10 cycles	4.00
P11 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	4.18
Stall cycles (UFS)	0.00
Nb insns	24.00
Nb uops	24.00
Nb loads	12.00
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.61
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	micro-operation queue, P2, P3, P11,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.00
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	0.31
Front-end cycles	4.00
DIV/SQRT cycles	2.20
P0 cycles	3.40
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	1.00
P4 cycles	2.20
P5 cycles	2.20
P6 cycles	1.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	2.20
P10 cycles	4.00
P11 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	4.18
Stall cycles (UFS)	0.00
Nb insns	24.00
Nb uops	24.00
Nb loads	12.00
Nb stores	2.00
Nb stack references	11.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.61
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.42

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.00 to 0.31 cycles (12.80x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with O2 or higher to enable loop vectorization and with ffast-math (included in Ofast) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.40 cycles (1.18x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	24
nb uops	24
loop length	109
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.20	2.20	4.00	4.00	1.00	2.20	2.20	1.00	1.00	1.00	2.20	4.00
cycles	2.20	3.40	4.00	4.00	1.00	2.20	2.20	1.00	1.00	1.00	2.20	4.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	4.18
Stall cycles	0.00

Cycles summary

Front-end	4.00
Dispatch	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.00 to 3.40 cycles (1.18x speedup).

ASM code

In the binary file, the address of the loop is: 641b6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
CMP -0x40(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
JE 640d0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 641a0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x2f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x118(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV (%RAX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL -0x100(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1
ADD -0x30(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
ADD -0x110(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (%RCX,%RAX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 64257 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with O2 or higher to enable loop vectorization and with ffast-math (included in Ofast) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

General properties

nb instructions	24
nb uops	24
loop length	109
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	11

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.20	2.20	4.00	4.00	1.00	2.20	2.20	1.00	1.00	1.00	2.20	4.00
cycles	2.20	3.40	4.00	4.00	1.00	2.20	2.20	1.00	1.00	1.00	2.20	4.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	4.18
Stall cycles	0.00

Cycles summary

Front-end	4.00
Dispatch	4.00
Overall L1	4.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.00 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 641b6

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
CMP -0x40(%RBP),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
LEA 0x1(%RAX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
JE 640d0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x220>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
CMPQ $0,-0x38(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 641a0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x2f0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0x108(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x118(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV (%RAX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL -0x100(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1
ADD -0x30(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
ADD -0x110(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV -0xf8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (%RCX,%RAX,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RSI,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV -0x68(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RAX,-0x160(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %ESI,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 64257 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x3a7>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code