OV - exec - Loop 1589 - libkripke.so

	Loop Id: 1589	Module: libkripke.so	Source: SweepSubdomain.cpp:87-105 [...]	Coverage: 0.08%

0xa4870 ADD	-0x70(%RBP),%RSI

0xa4874 MOV	-0x1e8(%RBP),%R8

0xa487b ADD	%R8,%RDX

0xa487e ADD	%R8,%RCX

0xa4881 ADD	%R8,%RAX

0xa4884 CMP	-0xe0(%RBP),%RDI

0xa488b LEA	0x1(%RDI),%RDI

0xa488f JE	a41e0

0xa4895 CMPQ	$0,-0x48(%RBP)

0xa489a JLE	a4870

0xa489c MOV	-0xd8(%RBP),%R8

0xa48a3 VMOVSD	(%R8),%XMM1

0xa48a8 MOV	-0xb8(%RBP),%R8

0xa48af IMUL	%RDI,%R8

0xa48b3 MOV	-0x40(%RBP),%R9

0xa48b7 ADD	%R8,%R9

0xa48ba ADD	-0x1e0(%RBP),%R8

0xa48c1 MOV	-0xf0(%RBP),%R10

0xa48c8 VMOVSD	(%R10),%XMM0

0xa48cd MOV	-0xd0(%RBP),%R10

0xa48d4 VMOVHPD	(%R10),%XMM0,%XMM2

0xa48d9 ADD	-0xc0(%RBP),%R8

0xa48e0 MOV	-0xe8(%RBP),%R10

0xa48e7 VMOVSD	(%R10,%R9,8),%XMM0

0xa48ed MOV	-0x60(%RBP),%R9

0xa48f1 VMOVHPD	(%R9),%XMM0,%XMM3

0xa48f6 VMOVSD	(%R12,%R8,8),%XMM0

0xa48fc VADDSD	%XMM1,%XMM1,%XMM1

0xa4900 VADDPD	%XMM2,%XMM2,%XMM2

0xa4904 VDIVPD	%XMM3,%XMM2,%XMM2

0xa4908 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

0xa490d VADDSD	%XMM3,%XMM2,%XMM3

0xa4911 XOR	%R9D,%R9D

0xa4914 XOR	%R10D,%R10D

0xa4917 MOV	-0x48(%RBP),%R11

0xa491b NOPL	(%RAX,%RAX,1)

  (1590) 0xa4920 VDIVSD	(%RBX,%R10,1),%XMM1,%XMM4

  (1590) 0xa4926 VMOVSD	(%RAX,%R9,1),%XMM5

  (1590) 0xa492c VFMADD231SD	%XMM4,%XMM0,%XMM5

  (1590) 0xa4931 VMOVSD	(%R13,%R10,1),%XMM6

  (1590) 0xa4938 VMOVSD	(%RSI,%R10,1),%XMM7

  (1590) 0xa493e VUNPCKLPD	%XMM7,%XMM6,%XMM8

  (1590) 0xa4942 VMULPD	%XMM2,%XMM8,%XMM8

  (1590) 0xa4946 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM9

  (1590) 0xa494c VADDSD	%XMM9,%XMM8,%XMM8

  (1590) 0xa4951 VADDSD	%XMM4,%XMM3,%XMM4

  (1590) 0xa4955 VADDSD	(%RCX,%R9,1),%XMM4,%XMM4

  (1590) 0xa495b VADDSD	%XMM5,%XMM8,%XMM5

  (1590) 0xa495f VDIVSD	%XMM4,%XMM5,%XMM4

  (1590) 0xa4963 VMOVSD	%XMM4,(%RDX,%R9,1)

  (1590) 0xa4969 VADDSD	%XMM4,%XMM4,%XMM4

  (1590) 0xa496d VSUBSD	%XMM6,%XMM4,%XMM5

  (1590) 0xa4971 VMOVSD	%XMM5,(%R13,%R10,1)

  (1590) 0xa4978 VSUBSD	%XMM7,%XMM4,%XMM5

  (1590) 0xa497c VMOVSD	%XMM5,(%RSI,%R10,1)

  (1590) 0xa4982 VSUBSD	%XMM0,%XMM4,%XMM0

  (1590) 0xa4986 ADD	%R15,%R10

  (1590) 0xa4989 ADD	%R14,%R9

  (1590) 0xa498c DEC	%R11

  (1590) 0xa498f JNE	a4920

0xa4991 VMOVSD	%XMM0,(%R12,%R8,8)

0xa4997 JMP	a4870

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

[...]

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.47
CQA speedup if FP arith vectorized	1.47
CQA speedup if fully vectorized	1.98
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:98-98,SweepSubdomain.cpp:103-103,forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	2.10
Front-end cycles	4.00
DIV/SQRT cycles	2.65
P0 cycles	2.75
P1 cycles	4.00
P2 cycles	4.00
P3 cycles	0.25
P4 cycles	2.75
P5 cycles	2.65
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	0.25
P9 cycles	2.70
P10 cycles	4.00
P11 cycles	2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	4.82 - 4.86
Stall cycles (UFS)	0.61 - 0.60
Nb insns	24.00
Nb uops	24.00
Nb loads	12.00
Nb stores	0.50
Nb stack references	8.50
FLOP/cycle	0.72
Nb FLOP add-sub	2.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.20
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	4.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	5.50
Stride indirect	0.00
Vectorization ratio all	8.33
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	8.33
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	16.67
Vector-efficiency ratio all	13.54
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	13.54
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.67
CQA speedup if FP arith vectorized	1.67
CQA speedup if fully vectorized	1.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P2, P3, P11,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:98-98,SweepSubdomain.cpp:103-103,forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.67
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	4.00
CQA cycles if fully vectorized	4.00
Front-end cycles	6.33
DIV/SQRT cycles	3.70
P0 cycles	3.90
P1 cycles	6.67
P2 cycles	6.67
P3 cycles	0.50
P4 cycles	3.90
P5 cycles	3.70
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	3.80
P10 cycles	6.67
P11 cycles	4.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	7.87 - 7.95
Stall cycles (UFS)	1.22 - 1.21
Nb insns	38.00
Nb uops	38.00
Nb loads	20.00
Nb stores	1.00
Nb stack references	13.00
FLOP/cycle	0.90
Nb FLOP add-sub	4.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	25.20
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	8.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	11.00
Stride indirect	0.00
Vectorization ratio all	16.67
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	16.67
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	33.33
Vector-efficiency ratio all	14.58
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	14.58
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	8.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-95,SweepSubdomain.cpp:98-98,SweepSubdomain.cpp:103-103,forall.hpp:59-59
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	1.67
CQA cycles if no scalar integer	1.67
CQA cycles if FP arith vectorized	1.67
CQA cycles if fully vectorized	0.21
Front-end cycles	1.67
DIV/SQRT cycles	1.60
P0 cycles	1.60
P1 cycles	1.33
P2 cycles	1.33
P3 cycles	0.00
P4 cycles	1.60
P5 cycles	1.60
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.60
P10 cycles	1.33
P11 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	1.77
Stall cycles (UFS)	0.00
Nb insns	10.00
Nb uops	10.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	4.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	19.20
Bytes prefetched	0.00
Bytes loaded	32.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	12.50
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	SweepSubdomain.cpp:87-105
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-88,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 4.17 to 2.10 cycles (1.98x speedup).

Details

8% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
8% of SSE/AVX addition or subtraction instructions are used in vector version.
16% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with O2 or higher to enable loop vectorization and with ffast-math (included in Ofast) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 3 FP arithmetical operations:

2: addition or subtraction
1: divide

The binary loop is loading 96 bytes (12 double precision FP elements). The binary loop is storing 4 bytes (0 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	24
loop length	115.50
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	8.50

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	4.00 cycles
front end	4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.65	2.75	4.00	4.00	0.25	2.75	2.65	0.25	0.25	0.25	2.70	4.00
cycles	2.65	2.75	4.00	4.00	0.25	2.75	2.65	0.25	0.25	0.25	2.70	4.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	2.00
Longest recurrence chain latency (RecMII)	1.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	4.82-4.86
Stall cycles	0.61-0.61
LM full (events)	1.28-1.25

Cycles summary

Front-end	4.00
Dispatch	4.13
DIV/SQRT	2.00
Data deps.	1.00
Overall L1	4.17

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	16%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

11% of peak load performance is reached (21.60 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.60 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	SweepSubdomain.cpp:87-105
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-88,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.67 to 4.00 cycles (1.67x speedup).

Details

16% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with O2 or higher to enable loop vectorization and with ffast-math (included in Ofast) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by reading data from caches/RAM (load units are a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.67 to 6.33 cycles (1.05x speedup).

Workaround

Read less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 11 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

4: addition or subtraction
2: divide

The binary loop is loading 160 bytes (20 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	38
nb uops	38
loop length	187
used x86 registers	11
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	13

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.33 cycles
front end	6.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.70	3.90	6.67	6.67	0.50	3.90	3.70	0.50	0.50	0.50	3.80	6.67
cycles	3.70	3.90	6.67	6.67	0.50	3.90	3.70	0.50	0.50	0.50	3.80	6.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	4.00
Longest recurrence chain latency (RecMII)	1.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	7.87-7.95
Stall cycles	1.22-1.21
LM full (events)	2.56-2.49

Cycles summary

Front-end	6.33
Dispatch	6.67
DIV/SQRT	4.00
Data deps.	1.00
Overall L1	6.67

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	25%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	100%

INT+FP

all	16%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	100%
other	33%

Vector efficiency ratios

INT

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	15%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	25%

INT+FP

all	14%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	25%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.67 cycles. At this rate:

12% of peak load performance is reached (24.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (1.20 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: a4895

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD -0x70(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV -0x1e8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %R8,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %R8,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
CMP -0xe0(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JE a41e0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x960>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
CMPQ $0,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE a4870 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xff0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0xd8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%R8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xb8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL %RDI,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
MOV -0x40(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %R8,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD -0x1e0(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV -0xf0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%R10),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xd0(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%R10),%XMM0,%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
ADD -0xc0(%RBP),%R8	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV -0xe8(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%R10,%R9,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x60(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%R9),%XMM0,%XMM3	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
VMOVSD (%R12,%R8,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD %XMM1,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VADDPD %XMM2,%XMM2,%XMM2	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VDIVPD %XMM3,%XMM2,%XMM2	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VSHUFPD $0x1,%XMM2,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
VADDSD %XMM3,%XMM2,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD %XMM0,(%R12,%R8,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
JMP a4870 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xff0>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	SweepSubdomain.cpp:87-105
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-88,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. 8 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 1.67 to 0.21 cycles (8.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with O2 or higher to enable loop vectorization and with ffast-math (included in Ofast) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 32 bytes.

General properties

nb instructions	10
nb uops	10
loop length	44
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.60	1.60	1.33	1.33	0.00	1.60	1.60	0.00	0.00	0.00	1.60	1.33
cycles	1.60	1.60	1.33	1.33	0.00	1.60	1.60	0.00	0.00	0.00	1.60	1.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	1.77
Stall cycles	0.00

Cycles summary

Front-end	1.67
Dispatch	1.60
Data deps.	1.00
Overall L1	1.67

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 1.67 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: a4895

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	P10	P11	Latency	Recip. throughput
ADD -0x70(%RBP),%RSI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33
MOV -0x1e8(%RBP),%R8	1	0	0	0.33	0.33	0	0	0	0.33	1	0.33
ADD %R8,%RDX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
ADD %R8,%RCX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
ADD %R8,%RAX	1	0.20	0.20	0	0	0.20	0.20	0.20	0	1	0.20
CMP -0xe0(%RBP),%RDI	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33
LEA 0x1(%RDI),%RDI	1	0	0	0	0	0	0	0	0	0	0.17
JE a41e0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x960>	1	0.50	0	0	0	0	0.50	0	0	0	0.50
CMPQ $0,-0x48(%RBP)	1	0.20	0.20	0.33	0.33	0.20	0.20	0.20	0.33	1	0.33
JLE a4870 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0xff0>	1	0.50	0	0	0	0	0.50	0	0	0	0.50

Report Configuration

Vectorization

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code