OV - exec - Loop 1590 - libkripke.so

	Loop Id: 1590	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 1.67%

0xa4920 VDIVSD	(%RBX,%R10,1),%XMM1,%XMM4    [6]

0xa4926 VMOVSD	(%RAX,%R9,1),%XMM5    [4]

0xa492c VFMADD231SD	%XMM4,%XMM0,%XMM5

0xa4931 VMOVSD	(%R13,%R10,1),%XMM6    [5]

0xa4938 VMOVSD	(%RSI,%R10,1),%XMM7    [2]

0xa493e VUNPCKLPD	%XMM7,%XMM6,%XMM8

0xa4942 VMULPD	%XMM2,%XMM8,%XMM8

0xa4946 VSHUFPD	$0x1,%XMM8,%XMM8,%XMM9

0xa494c VADDSD	%XMM9,%XMM8,%XMM8

0xa4951 VADDSD	%XMM4,%XMM3,%XMM4

0xa4955 VADDSD	(%RCX,%R9,1),%XMM4,%XMM4    [1]

0xa495b VADDSD	%XMM5,%XMM8,%XMM5

0xa495f VDIVSD	%XMM4,%XMM5,%XMM4

0xa4963 VMOVSD	%XMM4,(%RDX,%R9,1)    [3]

0xa4969 VADDSD	%XMM4,%XMM4,%XMM4

0xa496d VSUBSD	%XMM6,%XMM4,%XMM5

0xa4971 VMOVSD	%XMM5,(%R13,%R10,1)    [5]

0xa4978 VSUBSD	%XMM7,%XMM4,%XMM5

0xa497c VMOVSD	%XMM5,(%RSI,%R10,1)    [2]

0xa4982 VSUBSD	%XMM0,%XMM4,%XMM0

0xa4986 ADD	%R15,%R10

0xa4989 ADD	%R14,%R9

0xa498c DEC	%R11

0xa498f JNE	a4920

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

[...]

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	6.50 - 7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-87,SweepSubdomain.cpp:95-105,forall.hpp:59-59
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	26.00 - 28.00
CQA cycles if no scalar integer	26.00 - 28.00
CQA cycles if FP arith vectorized	11.92 - 12.83
CQA cycles if fully vectorized	4.00
Front-end cycles	4.17
DIV/SQRT cycles	2.00
P0 cycles	6.00
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.50
P4 cycles	6.00
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.40
P10 cycles	1.67
P11 cycles	8.00
Inter-iter dependencies cycles	26 - 28
FE+BE cycles (UFS)	26.82 - 29.06
Stall cycles (UFS)	21.85 - 24.09
Nb insns	24.00
Nb uops	23.00
Nb loads	5.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.54 - 0.50
Nb FLOP add-sub	8.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.29 - 2.46
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	10.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	2.18
CQA speedup if fully vectorized	6.50 - 7.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-87,SweepSubdomain.cpp:95-105,forall.hpp:59-59
Source loop unroll info	unrolled by 2
Source loop unroll confidence level	medium
Unroll/vectorization loop type	peel/tail
Unroll factor	1
CQA cycles	26.00 - 28.00
CQA cycles if no scalar integer	26.00 - 28.00
CQA cycles if FP arith vectorized	11.92 - 12.83
CQA cycles if fully vectorized	4.00
Front-end cycles	4.17
DIV/SQRT cycles	2.00
P0 cycles	6.00
P1 cycles	1.67
P2 cycles	1.67
P3 cycles	1.50
P4 cycles	6.00
P5 cycles	1.60
P6 cycles	1.50
P7 cycles	1.50
P8 cycles	1.50
P9 cycles	1.40
P10 cycles	1.67
P11 cycles	8.00
Inter-iter dependencies cycles	26 - 28
FE+BE cycles (UFS)	26.82 - 29.06
Stall cycles (UFS)	21.85 - 24.09
Nb insns	24.00
Nb uops	23.00
Nb loads	5.00
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.54 - 0.50
Nb FLOP add-sub	8.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	2.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.29 - 2.46
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	24.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	6.00
Stride indirect	0.00
Vectorization ratio all	10.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	50.00
Vector-efficiency ratio all	13.75
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	12.50
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

It is peel/tail loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)
2: divide

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	23
loop length	113
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	8.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	6.00	1.67	1.67	1.50	6.00	1.60	1.50	1.50	1.50	1.40	1.67
cycles	2.00	6.00	1.67	1.67	1.50	6.00	1.60	1.50	1.50	1.50	1.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	26.00-28.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	26.82-29.06
Stall cycles	21.85-24.09
RS full (events)	4.36-4.32
PRF_FLOAT full (events)	20.76-23.09

Cycles summary

Front-end	4.17
Dispatch	6.00
DIV/SQRT	8.00
Data deps.	26.00-28.00
Overall L1	26.00-28.00

Vectorization ratios

all	10%
load	0%
store	0%
mul	100%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	25%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

0% of peak load performance is reached (1.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: a4920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
VDIVSD (%RBX,%R10,1),%XMM1,%XMM4	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4
VMOVSD (%RAX,%R9,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD231SD %XMM4,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50
VMOVSD (%R13,%R10,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%RSI,%R10,1),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VUNPCKLPD %XMM7,%XMM6,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1
VMULPD %XMM2,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50
VSHUFPD $0x1,%XMM8,%XMM8,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
VADDSD %XMM9,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VADDSD %XMM4,%XMM3,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VADDSD (%RCX,%R9,1),%XMM4,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VADDSD %XMM5,%XMM8,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VDIVSD %XMM4,%XMM5,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD %XMM4,(%RDX,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VADDSD %XMM4,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VSUBSD %XMM6,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VMOVSD %XMM5,(%R13,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD %XMM7,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VMOVSD %XMM5,(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD %XMM0,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
DEC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JNE a4920 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x10a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

It is peel/tail loop of related source loop which is unrolled by 2 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-instr-generate, execute ,merge raw profiles with 'llvm-profdata merge -o default.profdata default.profraw' and recompile with -fprofile-instr-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 14 FP arithmetical operations:

9: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)
2: divide

The binary loop is loading 40 bytes (5 double precision FP elements). The binary loop is storing 24 bytes (3 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	24
nb uops	23
loop length	113
used x86 registers	11
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	8.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	6.00	1.67	1.67	1.50	6.00	1.60	1.50	1.50	1.50	1.40	1.67
cycles	2.00	6.00	1.67	1.67	1.50	6.00	1.60	1.50	1.50	1.50	1.40	1.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	8.00
Longest recurrence chain latency (RecMII)	26.00-28.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	26.82-29.06
Stall cycles	21.85-24.09
RS full (events)	4.36-4.32
PRF_FLOAT full (events)	20.76-23.09

Cycles summary

Front-end	4.17
Dispatch	6.00
DIV/SQRT	8.00
Data deps.	26.00-28.00
Overall L1	26.00-28.00

Vectorization ratios

all	10%
load	0%
store	0%
mul	100%
add-sub	0%
fma	0%
div/sqrt	0%
other	50%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	25%
add-sub	12%
fma	12%
div/sqrt	12%
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 28.00 cycles. At this rate:

0% of peak load performance is reached (1.43 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.86 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: a4920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
VDIVSD (%RBX,%R10,1),%XMM1,%XMM4	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4
VMOVSD (%RAX,%R9,1),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD231SD %XMM4,%XMM0,%XMM5	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50
VMOVSD (%R13,%R10,1),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%RSI,%R10,1),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VUNPCKLPD %XMM7,%XMM6,%XMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	1	1
VMULPD %XMM2,%XMM8,%XMM8	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	4	0.50
VSHUFPD $0x1,%XMM8,%XMM8,%XMM9	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
VADDSD %XMM9,%XMM8,%XMM8	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VADDSD %XMM4,%XMM3,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VADDSD (%RCX,%R9,1),%XMM4,%XMM4	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VADDSD %XMM5,%XMM8,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VDIVSD %XMM4,%XMM5,%XMM4	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD %XMM4,(%RDX,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VADDSD %XMM4,%XMM4,%XMM4	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VSUBSD %XMM6,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VMOVSD %XMM5,(%R13,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD %XMM7,%XMM4,%XMM5	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VMOVSD %XMM5,(%RSI,%R10,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD %XMM0,%XMM4,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %R14,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
DEC %R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JNE a4920 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x10a0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Report Configuration

Unrolling/vectorization cost

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Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

Execution units bottlenecks

FMA

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code