OV - exec - Loop 853 - libkripke.so

	Loop Id: 853	Module: libkripke.so	Source: forall.hpp:59-59 [...]	Coverage: 2.65%

0x4b4a0 LEA	(%RCX,%R13,1),%RSI

0x4b4a4 ADD	%R9,%RSI

0x4b4a7 VMOVUPD	(%RAX,%RCX,8),%YMM0    [7]

0x4b4ac VFMADD213PD	(%RDX,%RCX,8),%YMM8,%YMM0    [5]

0x4b4b2 ADD	%RDI,%RSI

0x4b4b5 LEA	(%RSI,%R8,1),%R10

0x4b4b9 VFMADD231PD	(%R12,%R10,8),%YMM9,%YMM0    [10]

0x4b4bf LEA	(%RSI,%R15,1),%R10

0x4b4c3 VFMADD231PD	(%R12,%R10,8),%YMM10,%YMM0    [3]

0x4b4c9 LEA	(%RSI,%RBX,1),%R10

0x4b4cd VFMADD231PD	(%R12,%R10,8),%YMM11,%YMM0    [4]

0x4b4d3 MOV	-0x168(%RBP),%R10    [9]

0x4b4da ADD	%RSI,%R10

0x4b4dd VFMADD231PD	(%R12,%R10,8),%YMM12,%YMM0    [1]

0x4b4e3 MOV	-0x160(%RBP),%R10    [9]

0x4b4ea ADD	%RSI,%R10

0x4b4ed VFMADD231PD	(%R12,%R10,8),%YMM13,%YMM0    [2]

0x4b4f3 MOV	-0x158(%RBP),%R10    [9]

0x4b4fa ADD	%RSI,%R10

0x4b4fd VFMADD231PD	(%R12,%R10,8),%YMM14,%YMM0    [6]

0x4b503 ADD	%R11,%RSI

0x4b506 VFMADD231PD	(%R12,%RSI,8),%YMM15,%YMM0    [8]

0x4b50c VMOVUPD	%YMM0,(%RDX,%RCX,8)    [5]

0x4b511 ADD	$0x4,%RCX

0x4b515 CMP	-0x2b8(%RBP),%RCX    [9]

0x4b51c JLE	4b4a0

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp: 62 - 62

--------------------------------------------------------------------------------

62:            phi(nm,g,z) += ell(nm, d) * psi(d, g, z);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, LTimesSdom const&, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	LTimes.cpp:62-62,forall.hpp:59-59
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	5.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	2.75
Front-end cycles	5.50
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	4.33
P2 cycles	4.33
P3 cycles	0.50
P4 cycles	2.40
P5 cycles	2.40
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.20
P10 cycles	4.33
P11 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	5.96
Stall cycles (UFS)	0.00
Nb insns	26.00
Nb uops	25.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	11.64
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	3.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.38
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	2.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.27
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, LTimesSdom const&, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	LTimes.cpp:62-62,forall.hpp:59-59
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	5.50
CQA cycles if no scalar integer	4.00
CQA cycles if FP arith vectorized	3.67
CQA cycles if fully vectorized	2.75
Front-end cycles	5.50
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	4.33
P2 cycles	4.33
P3 cycles	0.50
P4 cycles	2.40
P5 cycles	2.40
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.20
P10 cycles	4.33
P11 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	5.96
Stall cycles (UFS)	0.00
Nb insns	26.00
Nb uops	25.00
Nb loads	13.00
Nb stores	1.00
Nb stack references	4.00
FLOP/cycle	11.64
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	3.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	50.00
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, LTimesSdom const&, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 5.50 to 2.75 cycles (2.00x speedup).

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers). Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 32 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	25
loop length	126
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	4.33	4.33	0.50	2.40	2.40	0.50	0.50	0.50	2.20	4.33
cycles	4.00	4.00	4.33	4.33	0.50	2.40	2.40	0.50	0.50	0.50	2.20	4.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	5.96
Stall cycles	0.00

Cycles summary

Front-end	5.50
Dispatch	4.33
Data deps.	1.00
Overall L1	5.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

30% of peak load performance is reached (58.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.50 to 4.33 cycles (1.27x speedup).

ASM code

In the binary file, the address of the loop is: 4b4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LEA (%RCX,%R13,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R9,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VMOVUPD (%RAX,%RCX,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
VFMADD213PD (%RDX,%RCX,8),%YMM8,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
LEA (%RSI,%R8,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
LEA (%RSI,%R15,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM10,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
LEA (%RSI,%RBX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM11,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x168(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM12,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x160(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM13,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x158(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM14,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
ADD %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%RSI,8),%YMM15,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VMOVUPD %YMM0,(%RDX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP -0x2b8(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 4b4a0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0x9b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, LTimesSdom const&, Kripke::SdomId&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	libkripke.so

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/LTimes.cpp:62
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

It is main loop of related source loop which is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 4.00 cycles (1.37x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is vectorized, but using only 256 out of 512 bits (AVX/AVX2 instructions on AVX-512 processors).

By fully vectorizing your loop, you can lower the cost of an iteration from 5.50 to 2.75 cycles (2.00x speedup).

Details

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 32 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 2 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 2 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

8 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 64 FP arithmetical operations:

32: addition or subtraction (all inside FMA instructions)
32: multiply (all inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	26
nb uops	25
loop length	126
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	9
used zmm registers	0
nb stack references	4

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.50 cycles
front end	5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	4.00	4.33	4.33	0.50	2.40	2.40	0.50	0.50	0.50	2.20	4.33
cycles	4.00	4.00	4.33	4.33	0.50	2.40	2.40	0.50	0.50	0.50	2.20	4.33

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	5.96
Stall cycles	0.00

Cycles summary

Front-end	5.50
Dispatch	4.33
Data deps.	1.00
Overall L1	5.50

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	50%
load	50%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.50 cycles. At this rate:

30% of peak load performance is reached (58.18 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.82 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 4b4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LEA (%RCX,%R13,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R9,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VMOVUPD (%RAX,%RCX,8),%YMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.33
VFMADD213PD (%RDX,%RCX,8),%YMM8,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
LEA (%RSI,%R8,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM9,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
LEA (%RSI,%R15,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM10,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
LEA (%RSI,%RBX,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD (%R12,%R10,8),%YMM11,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x168(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM12,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x160(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM13,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x158(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
ADD %RSI,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%R10,8),%YMM14,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
ADD %R11,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VFMADD231PD (%R12,%RSI,8),%YMM15,%YMM0	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VMOVUPD %YMM0,(%RDX,%RCX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	0.50
ADD $0x4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP -0x2b8(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 4b4a0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE10LTimesSdomJRNS_6SdomIdERKNS_4Core3SetESB_SB_SB_RNS8_5FieldIdJNS_9DirectionENS_5GroupENS_4ZoneEEEERNSC_IdJNS_6MomentESE_SF_EEERNSC_IdJSI_SD_EEEEEEvT_RKT0_DpOT1_.extracted+0x9b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

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FMA

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Vector unaligned load/store instructions

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Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

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Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code