OV - exec - Function void PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ> >(Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_DGZ>, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Field<double, Kripke::Direction, Kripke::Group, Kripke::Zone>&, Kripke::Core::Field<double, Kripke::Direction>&, Kripke::Core::Field<double, Kripke::Zone>&, double*) const [clone .extracted]

	Function: void PopulationSdom::operator()<Kripke::ArchLayoutT<Kripke::ArchT_OpenMP, Kripke::LayoutT_ ...	Module: exec	Source: Collapse.hpp:81-89 [...]	Coverage: 0.38%

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp: 307 - 307

--------------------------------------------------------------------------------

307:     return Ret{lhs} + rhs;

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp: 79 - 79

--------------------------------------------------------------------------------

79:       : layout(V.layout), data(V.data)

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp: 74 - 262

--------------------------------------------------------------------------------

74:     val = operator_type::operator()(val, v);

[...]

261:       : parent{other.parent ? other.parent : &other},

262:         identity{other.identity},

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp: 81 - 89

--------------------------------------------------------------------------------

81: #pragma omp parallel for private(i0, i1) firstprivate(privatizer) \

82:     RAJA_COLLAPSE(2)

83:     for (i0 = 0; i0 < l0; ++i0) {

[...]

89:       }

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp: 253 - 253

--------------------------------------------------------------------------------

253:   CAMP_HOST_DEVICE constexpr tuple(tuple const& o) : base(o.base) {}

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp: 58 - 58

--------------------------------------------------------------------------------

58:           part_red += w(d) * psi(d,g,z) * volume(z);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp: 55 - 177

--------------------------------------------------------------------------------

55:       : val(rhs.val)

[...]

177:     return value_type(val + rhs);

0x454670 PUSH	%RBP

0x454671 MOV	%RSP,%RBP

0x454674 PUSH	%R15

0x454676 PUSH	%R14

0x454678 PUSH	%R13

0x45467a PUSH	%R12

0x45467c PUSH	%RBX

0x45467d SUB	$0x78,%RSP

0x454681 MOVL	$0,-0x38(%RBP)

0x454688 LEA	0x38(%R8),%RCX

0x45468c MOV	0x38(%R8),%RAX

0x454690 TEST	%RAX,%RAX

0x454693 CMOVNE	%RAX,%RCX

0x454697 TEST	%R9,%R9

0x45469a JS	4548ba

0x4546a0 MOV	%RDX,%RBX

0x4546a3 MOV	%RCX,-0x70(%RBP)

0x4546a7 MOV	(%R8),%RAX

0x4546aa MOV	%RAX,-0x98(%RBP)

0x4546b1 MOV	0x10(%R8),%RAX

0x4546b5 MOV	%RAX,-0x58(%RBP)

0x4546b9 MOV	0x20(%R8),%R14

0x4546bd MOV	0x28(%R8),%R15

0x4546c1 MOV	0x70(%R8),%RAX

0x4546c5 MOV	%RAX,-0x90(%RBP)

0x4546cc MOV	0x90(%R8),%RAX

0x4546d3 MOV	%RAX,-0x48(%RBP)

0x4546d7 MOV	0x98(%R8),%RAX

0x4546de MOV	%RAX,-0x40(%RBP)

0x4546e2 MOV	0xd8(%R8),%R12

0x4546e9 MOV	0x100(%R8),%R13

0x4546f0 VMOVSD	0x40(%R8),%XMM0

0x4546f6 VMOVSD	%XMM0,-0x30(%RBP)

0x4546fb MOV	(%RDI),%ESI

0x4546fd MOVQ	$0,-0x68(%RBP)

0x454705 MOV	%R9,-0x60(%RBP)

0x454709 MOVQ	$0x1,-0xa0(%RBP)

0x454714 SUB	$0x8,%RSP

0x454718 LEA	-0xa0(%RBP),%RAX

0x45471f LEA	0x2ad08a(%RIP),%RDI

0x454726 LEA	-0x38(%RBP),%RCX

0x45472a LEA	-0x68(%RBP),%R8

0x45472e LEA	-0x60(%RBP),%R9

0x454732 MOV	%ESI,-0x34(%RBP)

0x454735 MOV	$0x22,%EDX

0x45473a PUSH	$0x1

0x45473c PUSH	$0x1

0x45473e PUSH	%RAX

0x45473f CALL	402a70 <__kmpc_for_static_init_8@plt>

0x454744 ADD	$0x20,%RSP

0x454748 MOV	-0x68(%RBP),%RCX

0x45474c MOV	-0x60(%RBP),%RAX

0x454750 MOV	%RCX,-0x50(%RBP)

0x454754 CMP	%RAX,%RCX

0x454757 JA	4548c9

0x45475d MOV	%R15,%RSI

0x454760 SUB	%R14,%RSI

0x454763 JLE	4548c9

0x454769 MOV	-0x50(%RBP),%RDI

0x45476d LEA	0x1(%RDI),%RCX

0x454771 INC	%RAX

0x454774 CMP	%RAX,%RCX

0x454777 CMOVG	%RCX,%RAX

0x45477b NOT	%RDI

0x45477e ADD	%RAX,%RDI

0x454781 MOV	%RSI,-0x78(%RBP)

0x454785 AND	$-0x4,%RSI

0x454789 LEA	-0x1(%RSI),%R9

0x45478d LEA	(%R13,%R14,8),%R10

0x454792 MOV	-0x48(%RBP),%RAX

0x454796 LEA	(,%RAX,8),%RAX

0x45479e MOV	%RAX,-0x88(%RBP)

0x4547a5 MOV	-0x40(%RBP),%RAX

0x4547a9 LEA	(,%RAX,8),%RAX

0x4547b1 MOV	%RAX,-0x80(%RBP)

0x4547b5 XOR	%R11D,%R11D

0x4547b8 VMOVSD	-0x30(%RBP),%XMM4

0x4547bd JMP	4547d0

0x4547bf NOP

(1046) 0x4547c0 LEA	0x1(%R11),%RAX

(1046) 0x4547c4 CMP	%RDI,%R11

(1046) 0x4547c7 MOV	%RAX,%R11

(1046) 0x4547ca JE	4548ce

(1046) 0x4547d0 MOV	-0x50(%RBP),%RAX

(1046) 0x4547d4 ADD	%R11,%RAX

(1046) 0x4547d7 MOV	%RAX,%RCX

(1046) 0x4547da OR	%RBX,%RCX

(1046) 0x4547dd SHR	$0x20,%RCX

(1046) 0x4547e1 JE	4547f0

(1046) 0x4547e3 CQTO

(1046) 0x4547e5 IDIV	%RBX

(1046) 0x4547e8 JMP	4547f4

0x4547ea NOPW	(%RAX,%RAX,1)

(1046) 0x4547f0 XOR	%EDX,%EDX

(1046) 0x4547f2 DIV	%EBX

(1046) 0x4547f4 ADD	-0x98(%RBP),%RAX

(1046) 0x4547fb MOV	-0x90(%RBP),%RCX

(1046) 0x454802 VMOVSD	(%RCX,%RAX,8),%XMM0

(1046) 0x454807 TEST	%RSI,%RSI

(1046) 0x45480a JE	454880

(1046) 0x45480c MOV	-0x58(%RBP),%RCX

(1046) 0x454810 ADD	%RDX,%RCX

(1046) 0x454813 IMUL	-0x40(%RBP),%RCX

(1046) 0x454818 MOV	-0x48(%RBP),%R8

(1046) 0x45481c IMUL	%RAX,%R8

(1046) 0x454820 VBROADCASTSD	%XMM0,%YMM1

(1046) 0x454825 ADD	%R14,%RCX

(1046) 0x454828 ADD	%R8,%RCX

(1046) 0x45482b LEA	(%R12,%RCX,8),%R8

(1046) 0x45482f VXORPD	%XMM2,%XMM2,%XMM2

(1046) 0x454833 XOR	%ECX,%ECX

(1046) 0x454835 NOPW	%CS:(%RAX,%RAX,1)

  (1047) 0x454840 VMULPD	(%R8,%RCX,8),%YMM1,%YMM3

  (1047) 0x454846 VFMADD231PD	(%R10,%RCX,8),%YMM3,%YMM2

  (1047) 0x45484c ADD	$0x4,%RCX

  (1047) 0x454850 CMP	%R9,%RCX

  (1047) 0x454853 JLE	454840

(1046) 0x454855 VEXTRACTF128	$0x1,%YMM2,%XMM1

(1046) 0x45485b VADDPD	%XMM1,%XMM2,%XMM1

(1046) 0x45485f VSHUFPD	$0x1,%XMM1,%XMM1,%XMM2

(1046) 0x454864 VADDSD	%XMM2,%XMM1,%XMM1

(1046) 0x454868 VADDSD	%XMM1,%XMM4,%XMM4

(1046) 0x45486c MOV	%RSI,%R8

(1046) 0x45486f CMP	%RSI,-0x78(%RBP)

(1046) 0x454873 JE	4547c0

(1046) 0x454879 JMP	454883

0x45487b NOPL	(%RAX,%RAX,1)

(1046) 0x454880 XOR	%R8D,%R8D

(1046) 0x454883 ADD	%R14,%R8

(1046) 0x454886 IMUL	-0x88(%RBP),%RAX

(1046) 0x45488e ADD	-0x58(%RBP),%RDX

(1046) 0x454892 IMUL	-0x80(%RBP),%RDX

(1046) 0x454897 ADD	%RAX,%RDX

(1046) 0x45489a ADD	%R12,%RDX

(1046) 0x45489d NOPL	(%RAX)

  (1045) 0x4548a0 VMULSD	(%RDX,%R8,8),%XMM0,%XMM1

  (1045) 0x4548a6 VFMADD231SD	(%R13,%R8,8),%XMM1,%XMM4

  (1045) 0x4548ad INC	%R8

  (1045) 0x4548b0 CMP	%R8,%R15

  (1045) 0x4548b3 JNE	4548a0

(1046) 0x4548b5 JMP	4547c0

0x4548ba ADD	$0x78,%RSP

0x4548be POP	%RBX

0x4548bf POP	%R12

0x4548c1 POP	%R13

0x4548c3 POP	%R14

0x4548c5 POP	%R15

0x4548c7 POP	%RBP

0x4548c8 RET

0x4548c9 VMOVSD	-0x30(%RBP),%XMM4

0x4548ce VMOVSD	%XMM4,-0x30(%RBP)

0x4548d3 LEA	0x2acef6(%RIP),%RDI

0x4548da MOV	-0x34(%RBP),%ESI

0x4548dd VZEROUPPER

0x4548e0 CALL	402950 <__kmpc_for_static_fini@plt>

0x4548e5 LEA	0x2ad104(%RIP),%RDI

0x4548ec CALL	402a50 <__kmpc_global_thread_num@plt>

0x4548f1 MOV	%EAX,%EBX

0x4548f3 LEA	0x2ace76(%RIP),%RDI

0x4548fa MOV	$0x703200,%R14

0x454901 MOV	%EAX,%ESI

0x454903 MOV	%R14,%RDX

0x454906 CALL	402cb0 <__kmpc_critical@plt>

0x45490b MOV	-0x70(%RBP),%RAX

0x45490f VMOVSD	-0x30(%RBP),%XMM0

0x454914 VADDSD	0x10(%RAX),%XMM0,%XMM0

0x454919 VMOVSD	%XMM0,0x10(%RAX)

0x45491e LEA	0x2ace6b(%RIP),%RDI

0x454925 MOV	%EBX,%ESI

0x454927 MOV	%R14,%RDX

0x45492a ADD	$0x78,%RSP

0x45492e POP	%RBX

0x45492f POP	%R12

0x454931 POP	%R13

0x454933 POP	%R14

0x454935 POP	%R15

0x454937 POP	%RBP

0x454938 JMP	402aa0

0x45493d NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	Collapse.hpp:81-89
Module	exec

The function is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:74,261-262
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83,89
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp:253
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.67 to 3.00 cycles (6.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 20.67 to 1.61 cycles (12.86x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_critical@plt: 1 occurrences
__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_8@plt: 1 occurrences
__kmpc_global_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 176 bytes (22 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	124
loop length	481
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.67 cycles
front end	20.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.50	12.00	12.00	15.50	3.30	3.40	15.50	15.50	15.50	3.40	12.00
cycles	3.40	3.50	12.00	12.00	15.50	3.30	3.40	15.50	15.50	15.50	3.40	12.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	20.02-20.06
Stall cycles	0.00

Cycles summary

Front-end	20.67
Dispatch	15.50
Overall L1	20.67

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

4% of peak load performance is reached (8.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.67 to 15.50 cycles (1.33x speedup).

ASM code

In the binary file, the address of the function is: 454670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x38(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
JS 4548ba <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x24a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x10(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x20(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x28(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x70(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x90(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x98(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0xd8(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x100(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD 0x40(%R8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD %XMM0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x2ad08a(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
CALL 402a70 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JA 4548c9 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x259>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SUB %R14,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JLE 4548c9 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x259>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA 0x1(%RDI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
AND $-0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20
LEA -0x1(%RSI),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R13,%R14,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD -0x30(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
JMP 4547d0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x160>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
VMOVSD -0x30(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD %XMM4,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x2acef6(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL 402950 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
LEA 0x2ad104(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 402a50 <__kmpc_global_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
LEA 0x2ace76(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x703200,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 402cb0 <__kmpc_critical@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD 0x10(%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x2ace6b(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
JMP 402aa0 <__kmpc_end_critical@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Source file and lines	Collapse.hpp:81-89
Module	exec

The function is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Operators.hpp:307
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/View.hpp:79
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/pattern/detail/reduce.hpp:74,261-262
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/openmp/kernel/Collapse.hpp:81-83,89
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/tpl/camp/include/camp/tuple.hpp:253
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Population.cpp:58
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/internal/Iterators.hpp:55,177

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.67 to 3.00 cycles (6.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_critical@plt: 1 occurrences
__kmpc_for_static_fini@plt: 1 occurrences
__kmpc_for_static_init_8@plt: 1 occurrences
__kmpc_global_thread_num@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VZEROUPPER: 1 occurrences

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 176 bytes (22 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	119
nb uops	124
loop length	481
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	16

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.67 cycles
front end	20.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	3.40	3.50	12.00	12.00	15.50	3.30	3.40	15.50	15.50	15.50	3.40	12.00
cycles	3.40	3.50	12.00	12.00	15.50	3.30	3.40	15.50	15.50	15.50	3.40	12.00

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	20.02-20.06
Stall cycles	0.00

Cycles summary

Front-end	20.67
Dispatch	15.50
Overall L1	20.67

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Vector efficiency ratios

INT

all	11%
load	12%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.67 cycles. At this rate:

4% of peak load performance is reached (8.52 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (6.58 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 454670

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
SUB $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x38(%R8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV 0x38(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
TEST %RAX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
CMOVNE %RAX,%RCX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
TEST %R9,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20
JS 4548ba <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x24a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV (%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x10(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x20(%R8),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x28(%R8),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x70(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x90(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0x98(%R8),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV 0xd8(%R8),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV 0x100(%R8),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD 0x40(%R8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD %XMM0,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV (%RDI),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOVQ $0,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV %R9,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOVQ $0x1,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
LEA -0xa0(%RBP),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA 0x2ad08a(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x38(%RBP),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x68(%RBP),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA -0x60(%RBP),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV $0x22,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH $0x1	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
PUSH %RAX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50
CALL 402a70 <__kmpc_for_static_init_8@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
ADD $0x20,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x68(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x60(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RCX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JA 4548c9 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x259>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
SUB %R14,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
JLE 4548c9 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x259>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0x50(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA 0x1(%RDI),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
INC %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CMP %RAX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
CMOVG %RCX,%RAX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50
NOT %RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RAX,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %RSI,-0x78(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
AND $-0x4,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20
LEA -0x1(%RSI),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
LEA (%R13,%R14,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x48(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
MOV -0x40(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
LEA (,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVSD -0x30(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
JMP 4547d0 <_ZNK14PopulationSdomclIN6Kripke11ArchLayoutTINS1_12ArchT_OpenMPENS1_11LayoutT_DGZEEEEEvT_NS1_6SdomIdERKNS1_4Core3SetESB_SB_RNS8_5FieldIdJNS1_9DirectionENS1_5GroupENS1_4ZoneEEEERNSC_IdJSD_EEERNSC_IdJSF_EEEPd.extracted+0x160>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13
VMOVSD -0x30(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD %XMM4,-0x30(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x2acef6(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV -0x34(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1
CALL 402950 <__kmpc_for_static_fini@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
LEA 0x2ad104(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 402a50 <__kmpc_global_thread_num@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
LEA 0x2ace76(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x703200,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
CALL 402cb0 <__kmpc_critical@plt>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1
MOV -0x70(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD -0x30(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD 0x10(%RAX),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM0,0x10(%RAX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
LEA 0x2ace6b(%RIP),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %EBX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
ADD $0x78,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33
JMP 402aa0 <__kmpc_end_critical@plt>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17

Name	Coverage (%)	Time (s)
▼void PopulationSdom::operator() >(Kripke::ArchLayoutT, Kripke::SdomId, Kripke::Core::Set const&, Kripke::Core::Set const&, Kripke::Core::Set const&, K...–	0.38	0.23
▼Loop 1046 - Collapse.hpp:81-89 - exec–	0	0
○Loop 1047 - forall.hpp:59-59 - exec	0.38	0.23
○Loop 1045 - forall.hpp:59-59 - exec	0	0

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code