OV - exec - Loop 1130

	Loop Id: 1130	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 0.11%

0x45c2f0 LEA	0x1(%R10),%RAX

0x45c2f4 CMP	-0x38(%RBP),%R10

0x45c2f8 MOV	%RAX,%R10

0x45c2fb JE	45c220

0x45c301 CMPQ	$0,-0xf8(%RBP)

0x45c309 JLE	45c2f0

0x45c30b MOV	-0xe8(%RBP),%RAX

0x45c312 MOV	-0xf0(%RBP),%RCX

0x45c319 MOV	(%RAX,%RCX,8),%RCX

0x45c31d IMUL	-0xe0(%RBP),%RCX

0x45c325 ADD	-0x30(%RBP),%RCX

0x45c329 LEA	(%RDI,%RSI,1),%RAX

0x45c32d ADD	%R10,%RAX

0x45c330 ADD	%RCX,%RAX

0x45c333 VPBROADCASTQ	%RAX,%YMM1

0x45c339 MOV	-0x78(%RBP),%RAX

0x45c33d IMUL	%R10,%RAX

0x45c341 MOV	%RAX,-0x138(%RBP)

0x45c348 XOR	%R9D,%R9D

0x45c34b JMP	45c3a1

  (1131) 0x45c350 VXORPD	%XMM2,%XMM2,%XMM2

  (1131) 0x45c354 MOV	-0x138(%RBP),%RAX

  (1131) 0x45c35b ADD	%R9,%RAX

  (1131) 0x45c35e ADD	-0x128(%RBP),%RAX

  (1131) 0x45c365 MOV	-0x118(%RBP),%RDX

  (1131) 0x45c36c VMOVSD	(%RDX,%RAX,8),%XMM3

  (1131) 0x45c371 MOV	-0x130(%RBP),%RAX

  (1131) 0x45c378 ADD	%R9,%RAX

  (1131) 0x45c37b MOV	-0x120(%RBP),%RDX

  (1131) 0x45c382 VFMADD213SD	(%RDX,%RAX,8),%XMM2,%XMM3

  (1131) 0x45c388 VMOVSD	%XMM3,(%RDX,%RAX,8)

  (1131) 0x45c38d LEA	0x1(%R9),%RAX

  (1131) 0x45c391 CMP	-0x110(%RBP),%R9

  (1131) 0x45c398 MOV	%RAX,%R9

  (1131) 0x45c39b JE	45c2f0

  (1131) 0x45c3a1 MOV	-0x50(%RBP),%RAX

  (1131) 0x45c3a5 ADD	%R9,%RAX

  (1131) 0x45c3a8 MOVSXD	(%R14,%RAX,4),%R8

  (1131) 0x45c3ac TEST	%R8,%R8

  (1131) 0x45c3af JLE	45c350

  (1131) 0x45c3b1 MOV	-0x100(%RBP),%RDX

  (1131) 0x45c3b8 MOV	(%RDX,%RAX,8),%RDX

  (1131) 0x45c3bc ADD	%RDX,%R8

  (1131) 0x45c3bf LEA	0x1(%RDX),%RAX

  (1131) 0x45c3c3 CMP	%RAX,%R8

  (1131) 0x45c3c6 CMOVLE	%RAX,%R8

  (1131) 0x45c3ca MOV	%R8,%R13

  (1131) 0x45c3cd SUB	%RDX,%R13

  (1131) 0x45c3d0 MOV	%R13,%RAX

  (1131) 0x45c3d3 AND	$-0x4,%RAX

  (1131) 0x45c3d7 JE	45c460

  (1131) 0x45c3dd LEA	-0x1(%RAX),%R11

  (1131) 0x45c3e1 MOV	%RDX,%R14

  (1131) 0x45c3e4 LEA	(%R12,%RDX,8),%RDX

  (1131) 0x45c3e8 MOV	-0x58(%RBP),%RBX

  (1131) 0x45c3ec MOV	%R14,-0x108(%RBP)

  (1131) 0x45c3f3 LEA	(%RBX,%R14,8),%RBX

  (1131) 0x45c3f7 VXORPD	%XMM2,%XMM2,%XMM2

  (1131) 0x45c3fb XOR	%R14D,%R14D

  (1131) 0x45c3fe XCHG	%AX,%AX

    (1133) 0x45c400 VXORPS	%XMM3,%XMM3,%XMM3

    (1133) 0x45c404 VPMULLQ	(%RBX,%R14,8),%YMM0,%YMM3

    (1133) 0x45c40b VPADDQ	%YMM3,%YMM1,%YMM3

    (1133) 0x45c40f KXNORW	%K0,%K0,%K1

    (1133) 0x45c413 VXORPD	%XMM4,%XMM4,%XMM4

    (1133) 0x45c417 VGATHERQPD	(%R15,%YMM3,8),%YMM4{%K1}

    (1133) 0x45c41e VFMADD231PD	(%RDX,%R14,8),%YMM4,%YMM2

    (1133) 0x45c424 ADD	$0x4,%R14

    (1133) 0x45c428 CMP	%R11,%R14

    (1133) 0x45c42b JBE	45c400

  (1131) 0x45c42d VEXTRACTF128	$0x1,%YMM2,%XMM3

  (1131) 0x45c433 VADDPD	%XMM3,%XMM2,%XMM2

  (1131) 0x45c437 VSHUFPD	$0x1,%XMM2,%XMM2,%XMM3

  (1131) 0x45c43c VADDSD	%XMM3,%XMM2,%XMM2

  (1131) 0x45c440 CMP	%RAX,%R13

  (1131) 0x45c443 MOV	-0x40(%RBP),%R14

  (1131) 0x45c447 MOV	-0x58(%RBP),%R13

  (1131) 0x45c44b MOV	-0x48(%RBP),%RBX

  (1131) 0x45c44f MOV	-0x108(%RBP),%RDX

  (1131) 0x45c456 JE	45c354

  (1131) 0x45c45c JMP	45c46e

  (1131) 0x45c460 VXORPD	%XMM2,%XMM2,%XMM2

  (1131) 0x45c464 XOR	%EAX,%EAX

  (1131) 0x45c466 MOV	-0x58(%RBP),%R13

  (1131) 0x45c46a MOV	-0x48(%RBP),%RBX

  (1131) 0x45c46e ADD	%RDX,%RAX

  (1131) 0x45c471 NOPW	%CS:(%RAX,%RAX,1)

    (1132) 0x45c480 MOV	(%R13,%RAX,8),%RDX

    (1132) 0x45c485 IMUL	%RBX,%RDX

    (1132) 0x45c489 LEA	(%RCX,%RDI,1),%R11

    (1132) 0x45c48d ADD	%RSI,%R11

    (1132) 0x45c490 ADD	%R10,%R11

    (1132) 0x45c493 ADD	%RDX,%R11

    (1132) 0x45c496 VMOVSD	(%R15,%R11,8),%XMM3

    (1132) 0x45c49c VFMADD231SD	(%R12,%RAX,8),%XMM3,%XMM2

    (1132) 0x45c4a2 INC	%RAX

    (1132) 0x45c4a5 CMP	%RAX,%R8

    (1132) 0x45c4a8 JNE	45c480

  (1131) 0x45c4aa JMP	45c354

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp: 105 - 217

--------------------------------------------------------------------------------

105:     return TYPE(value + a);

[...]

217:     return (value < x.value);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp: 87 - 97

--------------------------------------------------------------------------------

87:             MixElem mix_start = zone_to_mixelem(z);

88:             MixElem mix_stop = mix_start + zone_to_num_mixelem(z);

89:

90:             double sigs_z = 0.0;

91:             for(MixElem mix = mix_start;mix < mix_stop;++ mix){

92:               Material mat = mixelem_to_material(mix);

93:               double fraction = mixelem_to_fraction(mix);

94:

95:               sigs_z += sigs(mat, n, global_g, global_gp) * fraction;

96:             }

97:             phi_out(nm, g, z) += sigs_z * phi(nm, gp, z);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp: 55 - 55

--------------------------------------------------------------------------------

55:     return a * b;

Path /

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.33
CQA cycles if no scalar integer	2.60
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	0.25
Front-end cycles	3.33
DIV/SQRT cycles	2.00
P0 cycles	3.00
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	0.50
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.00
P10 cycles	2.67
P11 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	3.53
Stall cycles (UFS)	0.00
Nb insns	20.00
Nb uops	20.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.60
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Metric	Value
CQA speedup if no scalar integer	1.28
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	13.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source	Scattering.cpp:95-97,forall.hpp:59-59,Layout.hpp:55-55
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.33
CQA cycles if no scalar integer	2.60
CQA cycles if FP arith vectorized	3.33
CQA cycles if fully vectorized	0.25
Front-end cycles	3.33
DIV/SQRT cycles	2.00
P0 cycles	3.00
P1 cycles	2.67
P2 cycles	2.67
P3 cycles	0.50
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	2.00
P10 cycles	2.67
P11 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	3.53
Stall cycles (UFS)	0.00
Nb insns	20.00
Nb uops	20.00
Nb loads	8.00
Nb stores	1.00
Nb stack references	8.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.60
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.25
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	10.94

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.60 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.33 to 0.25 cycles (13.33x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	20
nb uops	20
loop length	93
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	2.67	2.67	0.50	2.00	2.00	0.50	0.50	0.50	2.00	2.67
cycles	2.00	3.00	2.67	2.67	0.50	2.00	2.00	0.50	0.50	0.50	2.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.53
Stall cycles	0.00

Cycles summary

Front-end	3.33
Dispatch	3.00
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 3.33 to 3.00 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 45c301

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LEA 0x1(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP -0x38(%RBP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JE 45c220 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
CMPQ $0,-0xf8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 45c2f0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x2d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xf0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV (%RAX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL -0xe0(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1
ADD -0x30(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
LEA (%RDI,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 45c3a1 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x381>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84

Function	void Kripke::DispatchHelper::operator()&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&>(Kripke::LayoutT_DGZ, ScatteringSdom const&, Kripke::SdomId&, Kripke::SdomId&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Set&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&, Kripke::Core::Field&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/index/IndexValue.hpp:105,217
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/Scattering.cpp:87-97
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/util/Layout.hpp:55

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 2.60 cycles (1.28x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 64 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	20
nb uops	20
loop length	93
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	1
used zmm registers	0
nb stack references	8

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.33 cycles
front end	3.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	2.00	2.00	2.67	2.67	0.50	2.00	2.00	0.50	0.50	0.50	2.00	2.67
cycles	2.00	3.00	2.67	2.67	0.50	2.00	2.00	0.50	0.50	0.50	2.00	2.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Front-end and detailed OoO resources (UFS)

FE+BE cycles	3.53
Stall cycles	0.00

Cycles summary

Front-end	3.33
Dispatch	3.00
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.33 cycles. At this rate:

10% of peak load performance is reached (19.20 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.40 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 45c301

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LEA 0x1(%R10),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP -0x38(%RBP),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
MOV %RAX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JE 45c220 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x200>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
CMPQ $0,-0xf8(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
JLE 45c2f0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x2d0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50
MOV -0xe8(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xf0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV (%RAX,%RCX,8),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL -0xe0(%RBP),%RCX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1
ADD -0x30(%RBP),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
LEA (%RDI,%RSI,1),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
ADD %R10,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
VPBROADCASTQ %RAX,%YMM1	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1
MOV -0x78(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1
MOV %RAX,-0x138(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
XOR %R9D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 45c3a1 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE14ScatteringSdomJRNS_6SdomIdES7_RNS_4Core3SetESA_SA_RNS8_5FieldIdJNS_6MomentENS_5GroupENS_4ZoneEEEESG_RNSB_IdJNS_8MaterialENS_8LegendreENS_11GlobalGroupESJ_EEERNSB_INS_7MixElemEJSE_EEERNSB_IiJSE_EEERNSB_ISH_JSM_EEERNSB_IdJSM_EEERNSB_ISI_JSC_EEEEEEvT_RKT0_DpOT1_.extracted+0x381>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code