OV - exec - Loop 1287

	Loop Id: 1287	Module: exec	Source: forall.hpp:59-59 [...]	Coverage: 2.04%

0x46a0b0 VMOVSD	(%RSI,%R12,8),%XMM0    [8]

0x46a0b6 VADDSD	%XMM0,%XMM0,%XMM0

0x46a0ba MOV	-0x1f8(%RBP),%RDX    [11]

0x46a0c1 VDIVSD	(%RDX,%R9,1),%XMM0,%XMM0    [2]

0x46a0c7 VMOVSD	(%R14,%R12,8),%XMM1    [10]

0x46a0cd MOV	%RDI,%RDX

0x46a0d0 MOV	-0x210(%RBP),%RDI    [11]

0x46a0d7 VMOVHPD	(%RDI,%R12,8),%XMM1,%XMM1    [6]

0x46a0dd VADDPD	%XMM1,%XMM1,%XMM1

0x46a0e1 MOV	-0x218(%RBP),%RDI    [11]

0x46a0e8 MOV	-0xa0(%RBP),%RCX    [11]

0x46a0ef VMOVSD	(%RDI,%RCX,8),%XMM2    [4]

0x46a0f4 MOV	-0x208(%RBP),%RDI    [11]

0x46a0fb VMOVHPD	(%RDI,%R13,8),%XMM2,%XMM2    [13]

0x46a101 VDIVPD	%XMM2,%XMM1,%XMM1

0x46a105 VMOVSD	(%RDX,%RAX,8),%XMM2    [15]

0x46a10a MOV	-0x48(%RBP),%RCX    [11]

0x46a10e VFMADD213SD	(%RCX,%R11,1),%XMM0,%XMM2    [12]

0x46a114 MOV	-0x98(%RBP),%RCX    [11]

0x46a11b VFMADD231SD	(%RCX,%R9,1),%XMM1,%XMM2    [7]

0x46a121 VSHUFPD	$0x1,%XMM1,%XMM1,%XMM3

0x46a126 VFMADD231SD	(%R15,%R9,1),%XMM3,%XMM2    [5]

0x46a12c VADDSD	%XMM0,%XMM1,%XMM0

0x46a130 MOV	%R15,%RDI

0x46a133 MOV	%R13,%R15

0x46a136 MOV	%RCX,%R13

0x46a139 MOV	%R14,%RCX

0x46a13c MOV	%R8,%R14

0x46a13f MOV	%RSI,%R8

0x46a142 MOV	-0x50(%RBP),%RSI    [11]

0x46a146 VADDSD	(%RSI,%R11,1),%XMM3,%XMM1    [9]

0x46a14c MOV	%R8,%RSI

0x46a14f MOV	%R14,%R8

0x46a152 MOV	%RCX,%R14

0x46a155 MOV	%R13,%RCX

0x46a158 MOV	%R15,%R13

0x46a15b MOV	%RDI,%R15

0x46a15e MOV	%RDX,%RDI

0x46a161 VADDSD	%XMM0,%XMM1,%XMM0

0x46a165 VDIVSD	%XMM0,%XMM2,%XMM0

0x46a169 VMOVSD	%XMM0,(%R10,%R11,1)    [1]

0x46a16f VADDSD	%XMM0,%XMM0,%XMM0

0x46a173 VSUBSD	(%RDX,%RAX,8),%XMM0,%XMM1    [15]

0x46a178 VMOVSD	%XMM1,(%RDX,%RAX,8)    [15]

0x46a17d VSUBSD	(%RCX,%R9,1),%XMM0,%XMM1    [14]

0x46a183 VMOVSD	%XMM1,(%RCX,%R9,1)    [14]

0x46a189 VSUBSD	(%R15,%R9,1),%XMM0,%XMM0    [3]

0x46a18f VMOVSD	%XMM0,(%R15,%R9,1)    [3]

0x46a195 ADD	-0x200(%RBP),%R9    [11]

0x46a19c ADD	%R8,%R11

0x46a19f DEC	%RBX

0x46a1a2 JNE	46a0b0

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp: 87 - 105

--------------------------------------------------------------------------------

87:             double xcos_dxi = 2.0 * xcos(d) / dx(i);

88:             double ycos_dyj = 2.0 * ycos(d) / dy(j);

[...]

95:                 + psi_lf(d, g, j, k) * xcos_dxi

96:                 + psi_fr(d, g, i, k) * ycos_dyj

97:                 + psi_bo(d, g, i, j) * zcos_dzk)

98:                 / (xcos_dxi + ycos_dyj + zcos_dzk + sigt(g, z));

99:

100:             psi(d, g, z) = psi_d_g_z;

101:

102:             /* Apply diamond-difference relationships */

103:             psi_lf(d, g, j, k) = 2.0 * psi_d_g_z - psi_lf(d, g, j, k);

104:             psi_fr(d, g, i, k) = 2.0 * psi_d_g_z - psi_fr(d, g, i, k);

105:             psi_bo(d, g, i, j) = 2.0 * psi_d_g_z - psi_bo(d, g, i, j);

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp: 59 - 59

--------------------------------------------------------------------------------

59:   for (decltype(distance_it) i = 0; i < distance_it; ++i) {

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P0,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-105,forall.hpp:59-59
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	10.17
DIV/SQRT cycles	4.00
P0 cycles	7.00
P1 cycles	7.67
P2 cycles	7.67
P3 cycles	2.00
P4 cycles	7.00
P5 cycles	1.60
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	1.40
P10 cycles	7.67
P11 cycles	12.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	12.75 - 12.86
Stall cycles (UFS)	1.75 - 1.89
Nb insns	52.00
Nb uops	51.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	9.00
FLOP/cycle	1.67
Nb FLOP add-sub	10.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	9.00
Vectorization ratio all	10.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	11.11
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	33.33
Vector-efficiency ratio all	13.84
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	13.89
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	16.67
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.50
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P0,
Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source	SweepSubdomain.cpp:87-88,SweepSubdomain.cpp:95-105,forall.hpp:59-59
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	8.00
Front-end cycles	10.17
DIV/SQRT cycles	4.00
P0 cycles	7.00
P1 cycles	7.67
P2 cycles	7.67
P3 cycles	2.00
P4 cycles	7.00
P5 cycles	1.60
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	1.40
P10 cycles	7.67
P11 cycles	12.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	12.75 - 12.86
Stall cycles (UFS)	1.75 - 1.89
Nb insns	52.00
Nb uops	51.00
Nb loads	23.00
Nb stores	4.00
Nb stack references	9.00
FLOP/cycle	1.67
Nb FLOP add-sub	10.00
Nb FLOP mul	0.00
Nb FLOP fma	3.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	184.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	3.00
Stride indirect	9.00
Vectorization ratio all	10.71
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	11.11
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	33.33
Vectorization ratio other	33.33
Vector-efficiency ratio all	13.84
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	13.89
Vector-efficiency ratio fma	12.50
Vector-efficiency ratio div_sqrt	16.67
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-88,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.17 cycles (1.18x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

13 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 2 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 184 bytes (23 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	52
nb uops	51
loop length	248
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	7.00	7.67	7.67	2.00	7.00	1.60	2.00	2.00	2.00	1.40	7.67
cycles	4.00	7.00	7.67	7.67	2.00	7.00	1.60	2.00	2.00	2.00	1.40	7.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	2.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	12.75-12.86
Stall cycles	1.75-1.89
LB full (events)	2.40-2.52

Cycles summary

Front-end	10.17
Dispatch	7.67
DIV/SQRT	12.00
Data deps.	2.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	33%
other	100%

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	33%
other	33%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	12%
div/sqrt	16%
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	12%
div/sqrt	16%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

7% of peak load performance is reached (15.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46a0b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
VMOVSD (%RSI,%R12,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD %XMM0,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV -0x1f8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VDIVSD (%RDX,%R9,1),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4
VMOVSD (%R14,%R12,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x210(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%RDI,%R12,8),%XMM1,%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
VADDPD %XMM1,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV -0x218(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%RDI,%RCX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x208(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%RDI,%R13,8),%XMM2,%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
VDIVPD %XMM2,%XMM1,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD (%RDX,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD213SD (%RCX,%R11,1),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x98(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD231SD (%RCX,%R9,1),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
VFMADD231SD (%R15,%R9,1),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD (%RSI,%R11,1),%XMM3,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
VADDSD %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VDIVSD %XMM0,%XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD %XMM0,(%R10,%R11,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VADDSD %XMM0,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VSUBSD (%RDX,%RAX,8),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM1,(%RDX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD (%RCX,%R9,1),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM1,(%RCX,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD (%R15,%R9,1),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM0,(%R15,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
ADD -0x200(%RBP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JNE 46a0b0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Function	void Kripke::DispatchHelper::operator()(Kripke::LayoutT_DGZ, SweepSdom const&, Kripke::Core::DataStore&, Kripke::SdomId&) const [clone .extracted]
Source file and lines	forall.hpp:59-59
Module	exec

The loop is defined in:

/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/src/Kripke/Kernel/SweepSubdomain.cpp:87-88,95-105
/scratch_na/users/xoserete/qaas_runs/171-319-6990/intel/Kripke/build/Kripke/tpl/raja/include/RAJA/policy/loop/forall.hpp:59

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

10% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
11% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX fused multiply-add instructions are used in vector version.
33% of SSE/AVX divide and square root instructions are used in vector version.
33% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ffast-math (included in Ofast) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

FMA

Detected 3 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 3 occurrence(s)
Irregular (variable stride) or indirect: 9 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
3: multiply (all inside FMA instructions)
4: divide

The binary loop is loading 184 bytes (23 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

Unroll opportunity

Loop is potentially data access bound.

Workaround

General properties

nb instructions	52
nb uops	51
loop length	248
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	9

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.17 cycles
front end	10.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	4.00	7.00	7.67	7.67	2.00	7.00	1.60	2.00	2.00	2.00	1.40	7.67
cycles	4.00	7.00	7.67	7.67	2.00	7.00	1.60	2.00	2.00	2.00	1.40	7.67

Execution ports to units layout:

P0 (256 bits): VPU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	12.00
Longest recurrence chain latency (RecMII)	2.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	12.75-12.86
Stall cycles	1.75-1.89
LB full (events)	2.40-2.52

Cycles summary

Front-end	10.17
Dispatch	7.67
DIV/SQRT	12.00
Data deps.	2.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	33%
other	100%

INT+FP

all	10%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	0%
div/sqrt	33%
other	33%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	12%
div/sqrt	16%
other	25%

INT+FP

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	13%
fma	12%
div/sqrt	16%
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

7% of peak load performance is reached (15.33 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46a0b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
VMOVSD (%RSI,%R12,8),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD %XMM0,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV -0x1f8(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VDIVSD (%RDX,%R9,1),%XMM0,%XMM0	1	1	0	0.33	0.33	0	0	0	0	0	0	0	0.33	13-15	4
VMOVSD (%R14,%R12,8),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV %RDI,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x210(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%RDI,%R12,8),%XMM1,%XMM1	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
VADDPD %XMM1,%XMM1,%XMM1	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV -0x218(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0xa0(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVSD (%RDI,%RCX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x208(%RBP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VMOVHPD (%RDI,%R13,8),%XMM2,%XMM2	1	0	0	0.33	0.33	0	1	0	0	0	0	0	0.33	4-12	1
VDIVPD %XMM2,%XMM1,%XMM1	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD (%RDX,%RAX,8),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
MOV -0x48(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD213SD (%RCX,%R11,1),%XMM0,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
MOV -0x98(%RBP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VFMADD231SD (%RCX,%R9,1),%XMM1,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VSHUFPD $0x1,%XMM1,%XMM1,%XMM3	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50
VFMADD231SD (%R15,%R9,1),%XMM3,%XMM2	1	0.50	0.50	0.33	0.33	0	0	0	0	0	0	0	0.33	4	0.50
VADDSD %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R13,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R8,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RSI,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV -0x50(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33
VADDSD (%RSI,%R11,1),%XMM3,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
MOV %R8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R14,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R13,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %R15,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
MOV %RDX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
VADDSD %XMM0,%XMM1,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VDIVSD %XMM0,%XMM2,%XMM0	1	1	0	0	0	0	0	0	0	0	0	0	0	13-15	4
VMOVSD %XMM0,(%R10,%R11,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VADDSD %XMM0,%XMM0,%XMM0	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	3	0.50
VSUBSD (%RDX,%RAX,8),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM1,(%RDX,%RAX,8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD (%RCX,%R9,1),%XMM0,%XMM1	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM1,(%RCX,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
VSUBSD (%R15,%R9,1),%XMM0,%XMM0	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50
VMOVSD %XMM0,(%R15,%R9,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50
ADD -0x200(%RBP),%R9	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33
ADD %R8,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20
DEC %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17
JNE 46a0b0 <_ZNK6Kripke14DispatchHelperINS_12ArchT_OpenMPEEclINS_11LayoutT_DGZE9SweepSdomJRNS_4Core9DataStoreERNS_6SdomIdEEEEvT_RKT0_DpOT1_.extracted+0x760>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code