OV - K-Means scalability gcc-O3-all 100000000 - Loop 3

	Loop Id: 3	Module: kmeans-gcc-O3-all	Source: main.cpp:115-122	Coverage: 5.66%

0x401dec ANDS	W8, W6, #64

0x401df0 LDP	D27, D28, [X18]

0x401df4 FMOV	D30, D26

0x401df8 ORR	X16, XZR, X10

0x401dfc MOVZ	W13, #0

0x401e00 B.EQ	401ea0

0x401e04 CMP	W8, #1

0x401e08 B.EQ	401e6c

0x401e0c CMP	W8, #2

0x401e10 B.EQ	401e40

0x401e14 LDP	D31, D29, [X10]

0x401e18 FSUB	D0, D28, S29

0x401e1c FSUB	D1, D27, S31

0x401e20 FMUL	D2, D0, D0

0x401e24 FMADD	D3, D1, D1, D2

0x401e28 FCMPE	D26, D3

0x401e2c B.LS	401e38

0x401e30 FMOV	D30, D3

0x401e34 STR	WZR, [X7, X4,LSL #2]

0x401e38 MOVZ	W13, #1

0x401e3c ADD	X16, X10, #16

0x401e40 LDP	D4, D5, [X16]

0x401e44 FSUB	D6, D28, S5

0x401e48 FSUB	D7, D27, S4

0x401e4c FMUL	D16, D6, D6

0x401e50 FMADD	D17, D7, D7, D16

0x401e54 FCMPE	D30, D17

0x401e58 B.LS	401e64

0x401e5c FMOV	D30, D17

0x401e60 STR	W13, [X7, X4,LSL #2]

0x401e64 ADD	W13, W13, #1

0x401e68 ADD	X16, X16, #16

0x401e6c LDP	D18, D19, [X16]

0x401e70 FSUB	D20, D28, S19

0x401e74 FSUB	D21, D27, S18

0x401e78 FMUL	D22, D20, D20

0x401e7c FMADD	D23, D21, D21, D22

0x401e80 FCMPE	D30, D23

0x401e84 B.LS	401e90

0x401e88 FMOV	D30, D23

0x401e8c STR	W13, [X7, X4,LSL #2]

0x401e90 ADD	W13, W13, #1

0x401e94 ADD	X16, X16, #16

0x401e98 CMP	W6, W13

0x401e9c B.EQ	401f54

  (2) 0x401ea0 LDP	D24, D25, [X16]

  (2) 0x401ea4 ADD	X11, X16, #16

  (2) 0x401ea8 ADD	W12, W13, #1

  (2) 0x401eac FSUB	D29, D28, S25

  (2) 0x401eb0 FSUB	D31, D27, S24

  (2) 0x401eb4 FMUL	D0, D29, D29

  (2) 0x401eb8 FMADD	D1, D31, D31, D0

  (2) 0x401ebc FCMPE	D30, D1

  (2) 0x401ec0 B.LS	401ecc

  (2) 0x401ec4 FMOV	D30, D1

  (2) 0x401ec8 STR	W13, [X7, X4,LSL #2]

  (2) 0x401ecc LDR	D4, [X11, #8]

  (2) 0x401ed0 LDR	D2, [X16, #16]

  (2) 0x401ed4 FSUB	D5, D28, S4

  (2) 0x401ed8 FSUB	D3, D27, S2

  (2) 0x401edc FMUL	D6, D5, D5

  (2) 0x401ee0 FMADD	D7, D3, D3, D6

  (2) 0x401ee4 FCMPE	D30, D7

  (2) 0x401ee8 B.LS	401ef4

  (2) 0x401eec FMOV	D30, D7

  (2) 0x401ef0 STR	W12, [X7, X4,LSL #2]

  (2) 0x401ef4 LDP	D16, D17, [X11, #16]

  (2) 0x401ef8 ADD	W13, W12, #3

  (2) 0x401efc ADD	W14, W12, #1

  (2) 0x401f00 ADD	W15, W12, #2

  (2) 0x401f04 ADD	X16, X11, #48

  (2) 0x401f08 FSUB	D18, D28, S17

  (2) 0x401f0c FSUB	D19, D27, S16

  (2) 0x401f10 FMUL	D20, D18, D18

  (2) 0x401f14 FMADD	D21, D19, D19, D20

  (2) 0x401f18 FCMPE	D30, D21

  (2) 0x401f1c B.LS	401f28

  (2) 0x401f20 FMOV	D30, D21

  (2) 0x401f24 STR	W14, [X7, X4,LSL #2]

  (2) 0x401f28 LDP	D22, D23, [X11, #32]

  (2) 0x401f2c FSUB	D24, D28, S23

  (2) 0x401f30 FSUB	D25, D27, S22

  (2) 0x401f34 FMUL	D29, D24, D24

  (2) 0x401f38 FMADD	D31, D25, D25, D29

  (2) 0x401f3c FCMPE	D30, D31

  (2) 0x401f40 B.LS	401f4c

  (2) 0x401f44 FMOV	D30, D31

  (2) 0x401f48 STR	W15, [X7, X4,LSL #2]

  (2) 0x401f4c CMP	W6, W13

  (2) 0x401f50 B.NE	401ea0

0x401f54 ADD	X4, X4, #1

0x401f58 ADD	X18, X18, #16

0x401f5c CMP	W17, W4

0x401f60 B.GT	401dec

/home/fmusial/KMEANS_Benchmarks/kmeans/main.cpp: 115 - 122

--------------------------------------------------------------------------------

115:             double optimal_dist = DBL_MAX;

116:             for (int j = 0; j < k; ++j) {

117:                 double dist =

118:                     (points[i].x - centroids[j].x) * (points[i].x - centroids[j].x) +

119:                     (points[i].y - centroids[j].y) * (points[i].y - centroids[j].y);

120:                 if (dist < optimal_dist) {

121:                     optimal_dist = dist;

122:                     assignment[i] = j;

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

Coverage (%)	Name	Source Location	Module
►50.03+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all
►49.97+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6

Coverage (%)	Name	Source Location	Module
►74.00+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►26.00+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

Coverage (%)	Name	Source Location	Module
►85.19+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►14.81+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

Coverage (%)	Name	Source Location	Module
►92.15+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►7.85+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

Coverage (%)	Name	Source Location	Module
►96.59+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►3.41+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

Coverage (%)	Name	Source Location	Module
►97.81+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	pthread_condattr_setpshared		libc.so.6
○	__clone		libc.so.6
►2.19+	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	k_means(int, point_t*, point_t[...]	main.cpp:126	kmeans-gcc-O3-all
○	main	main.cpp:29	kmeans-gcc-O3-all
○	__libc_init_first		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	kmeans-gcc-O3-all

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	4.59
CQA speedup if FP arith vectorized	2.02
CQA speedup if fully vectorized	5.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	k_means(int, point_t, point_t, int*, int, int) [clone ._omp_fn.0]
Source	main.cpp:115-122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.13
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.03
CQA cycles if fully vectorized	1.19
Front-end cycles	6.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	4.75
P9 cycles	4.75
P10 cycles	2.50
P11 cycles	2.17
P12 cycles	2.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.45
Nb FLOP add-sub	6.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.41
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.76
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.90
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.23

Metric	Value
CQA speedup if no scalar integer	4.59
CQA speedup if FP arith vectorized	2.02
CQA speedup if fully vectorized	5.16
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	k_means(int, point_t, point_t, int*, int, int) [clone ._omp_fn.0]
Source	main.cpp:115-122
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.13
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	3.03
CQA cycles if fully vectorized	1.19
Front-end cycles	6.13
P0 cycles	4.00
P1 cycles	4.00
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	3.75
P6 cycles	4.75
P7 cycles	4.75
P8 cycles	4.75
P9 cycles	4.75
P10 cycles	2.50
P11 cycles	2.17
P12 cycles	2.33
P13 cycles	1.50
P14 cycles	1.50
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	49.00
Nb uops	49.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	2.45
Nb FLOP add-sub	6.00
Nb FLOP mul	3.00
Nb FLOP fma	3.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.41
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	11.76
Vectorization ratio load	100.00
Vectorization ratio store	0.00
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.90
Vector-efficiency ratio load	50.00
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	25.00
Vector-efficiency ratio add_sub	21.88
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	19.23

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	k_means(int, point_t, point_t, int*, int, int) [clone ._omp_fn.0]
Source file and lines	main.cpp:115-122
Module	kmeans-gcc-O3-all

The loop is defined in /home/fmusial/KMEANS_Benchmarks/kmeans/main.cpp:115-122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 254 paths individually, rerun with max-paths=254
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 254 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 1.33 cycles (4.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 6.13 to 1.19 cycles (5.16x speedup).

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

9: addition or subtraction (3 inside FMA instructions)
6: multiply (3 inside FMA instructions)

The binary loop is loading 64 bytes. The binary loop is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	6
used x registers	6
used b registers	0
used h registers	0
used s registers	6
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	3.75	3.75	3.75	3.75	4.75	4.75	4.75	4.75	2.50	2.17	2.33	1.50	1.50
cycles	4.00	4.00	3.75	3.75	3.75	3.75	4.75	4.75	4.75	4.75	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	4.75
Overall L1	6.13

Vectorization ratios

INT

all	26%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	100%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	22%
load	50%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	50%
store	12%
mul	25%
add-sub	21%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.13 cycles. At this rate:

10% of peak load performance is reached (10.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (1.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 6.13 to 4.75 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 401dec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ANDS W8, W6, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDP D27, D28, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMOV D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X16, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 401ea0 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401e6c <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401e40 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D31, D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D0, D28, S29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D1, D27, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D3, D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D26, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e38 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR WZR, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D4, D5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D6, D28, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D27, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D17, D7, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D30, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e64 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR W13, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D18, D19, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D20, D28, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D21, D27, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D23, D21, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D30, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e90 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR W13, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401f54 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 401dec <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	k_means(int, point_t, point_t, int*, int, int) [clone ._omp_fn.0]
Source file and lines	main.cpp:115-122
Module	kmeans-gcc-O3-all

The loop is defined in /home/fmusial/KMEANS_Benchmarks/kmeans/main.cpp:115-122.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 254 paths individually, rerun with max-paths=254
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.13 to 1.33 cycles (4.59x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

11% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 15 FP arithmetical operations:

9: addition or subtraction (3 inside FMA instructions)
6: multiply (3 inside FMA instructions)

The binary loop is loading 64 bytes. The binary loop is storing 12 bytes.

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	49
nb uops	49
loop length	196
used w registers	6
used x registers	6
used b registers	0
used h registers	0
used s registers	6
used d registers	22
used q registers	0
used v registers	0
used z registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	6.13 cycles
front end	6.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	3.75	3.75	3.75	3.75	4.75	4.75	4.75	4.75	2.50	2.17	2.33	1.50	1.50
cycles	4.00	4.00	3.75	3.75	3.75	3.75	4.75	4.75	4.75	4.75	2.50	2.17	2.33	1.50	1.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.13
Dispatch	4.75
Overall L1	6.13

Vectorization ratios

INT

all	26%
load	100%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	100%
store	0%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	22%
load	50%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	25%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	25%
add-sub	25%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	23%
load	50%
store	12%
mul	25%
add-sub	21%
fma	25%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.13 cycles. At this rate:

10% of peak load performance is reached (10.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (1.96 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 401dec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ANDS W8, W6, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
LDP D27, D28, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FMOV D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
ORR X16, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
B.EQ 401ea0 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x120>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401e6c <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401e40 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D31, D29, [X10]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D0, D28, S29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D1, D27, S31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D2, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D3, D1, D1, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D26, D3	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e38 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR WZR, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X10, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D4, D5, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D6, D28, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D7, D27, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D16, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D17, D7, D7, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D30, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e64 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0xe4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR W13, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDP D18, D19, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (50.0%)
FSUB D20, D28, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FSUB D21, D27, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (25.0%)
FMADD D23, D21, D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (25.0%)
FCMPE D30, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (25.0%)
B.LS 401e90 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x110>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D30, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (25.0%)
STR W13, [X7, X4,LSL #2]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (12.5%)
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (12.5%)
ADD X16, X16, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W6, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
B.EQ 401f54 <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x1d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X18, X18, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
CMP W17, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.GT 401dec <_Z7k_meansiP7point_tS0_Piii._omp_fn.0+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

▶Scalability Runs Description

Run run_1_thread	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PROC_BIND: closeOMP_NUM_THREADS: 1OMP_PLACES: cores
Run run_2_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PLACES: coresOMP_PROC_BIND: closeOMP_NUM_THREADS: 2
Run run_4_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PLACES: coresOMP_PROC_BIND: closeOMP_NUM_THREADS: 4
Run run_8_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PLACES: coresOMP_PROC_BIND: closeOMP_NUM_THREADS: 8
Run run_16_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PLACES: coresOMP_PROC_BIND: closeOMP_NUM_THREADS: 16
Run run_32_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PROC_BIND: closeOMP_PLACES: coresOMP_NUM_THREADS: 32
Run run_64_threads	Number processes: 1Number nodes: 1Run Command: <executable> kmeans/input/100000000.in 1000 100000000 50 25MPI Command: Dataset: Run Directory: /home/fmusial/KMEANS_BenchmarksOMP_PROC_BIND: closeOMP_PLACES: coresOMP_NUM_THREADS: 64

(run_1_thread) Efficiency	(run_1_thread) Potential Speed-Up (%)	(run_2_threads) Efficiency	(run_2_threads) Potential Speed-Up (%)	(run_4_threads) Efficiency	(run_4_threads) Potential Speed-Up (%)	(run_8_threads) Efficiency	(run_8_threads) Potential Speed-Up (%)	(run_16_threads) Efficiency	(run_16_threads) Potential Speed-Up (%)	(run_32_threads) Efficiency	(run_32_threads) Potential Speed-Up (%)	(run_64_threads) Efficiency	(run_64_threads) Potential Speed-Up (%)
1	0	0.94	0.35	0.95	0.31	0.92	0.47	0.89	0.68	0.91	0.5	1.3	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
run_1_thread	1	1	1	1	8.0649995803833	5.6638226509094
run_2_threads	2	0.94	1.88	2	4.2299990653992	5.9248099327087
run_4_threads	4	0.95	3.79	4	2.2349998950958	5.7662057876587
run_8_threads	8	0.92	7.37	8	1.2450000047684	5.8710536956787
run_16_threads	16	0.89	14.21	16	0.67500007152557	6.0438780784607
run_32_threads	32	0.91	29.19	32	0.34499999880791	5.6615009307861
run_64_threads	64	1.3	83.34	64	0.17500001192093	4.7905330657959

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency