OV - - Loop 23865 - engine_linuxa64

	Loop Id: 23865	Module: engine_linuxa64_ompi	Source: r4cum3p.F:115-131	Coverage: 0.03%

0x82cda0 LDR	D0, [X2], #12    [4]

0x82cda4 LDR	D1, [X22], #8    [15]

0x82cda8 LDR	D2, [X14], #8    [12]

0x82cdac SSHLL	V0.2D, V0.2S, #26

0x82cdb0 LDR	D3, [X21], #8    [14]

0x82cdb4 FNEG	D5, D2

0x82cdb8 FNEG	D6, D3

0x82cdbc SUBS	X6, X6, #1

0x82cdc0 STR	D1, [X5], #8    [1]

0x82cdc4 STR	D2, [X3], #8    [13]

0x82cdc8 STR	D3, [X13], #8    [9]

0x82cdcc MOV	X15, V0.D[1]

0x82cdd0 FMOV	X17, D0

0x82cdd4 LDP	D0, D4, [X16, #1016]    [2]

0x82cdd8 STR	D5, [X12], #8    [8]

0x82cddc STR	D6, [X18], #8    [3]

0x82cde0 ADD	X16, X16, #24

0x82cde4 STR	D1, [X8, X17]    [6]

0x82cde8 STR	D2, [X9, X17]    [7]

0x82cdec STR	D3, [X11, X17]    [11]

0x82cdf0 STR	D0, [X0, X17]    [10]

0x82cdf4 FNEG	D0, D1

0x82cdf8 STR	D5, [X9, X15]    [7]

0x82cdfc STR	D6, [X11, X15]    [11]

0x82ce00 STR	D4, [X0, X15]    [10]

0x82ce04 STR	D0, [X10], #8    [5]

0x82ce08 STR	D0, [X8, X15]    [6]

0x82ce0c B.NE	82cda0

/home/hbollore/pop3/openradioss/OpenRadioss/engine/source/elements/spring/r4cum3p.F: 115 - 131

--------------------------------------------------------------------------------

115:          N = IADR(1,II)

116:          FSKY(1,N)=F11(I)

117:          FSKY(2,N)=F21(I)

118:          FSKY(3,N)=F31(I)

119:          FX1(I) = -F11(I)

120:          FY1(I) = -F21(I)

121:          FZ1(I) = -F31(I)

122:          FSKY(7,N)=STI(1,I)

123:          N = IADR(2,II)

124:          FSKY(1,N)=-F11(I)

125:          FSKY(2,N)=-F21(I)

126:          FSKY(3,N)=-F31(I)

127:          FX2(I) = F11(I)

128:          FY2(I) = F21(I)

129:          FZ2(I) = F31(I)

130:          FSKY(7,N)=STI(2,I)

131:         ENDDO

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9,
Function	r4cum3p
Source	r4cum3p.F:115-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	4.00
Front-end cycles	3.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	5.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	14.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	112.00
Stride 0	10.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	7.69
Vectorization ratio load	20.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	51.92
Vector-efficiency ratio load	60.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.88
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P8, P9,
Function	r4cum3p
Source	r4cum3p.F:115-131
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	4.00
Front-end cycles	3.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.08
P3 cycles	2.08
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	1.92
P7 cycles	1.92
P8 cycles	7.50
P9 cycles	7.50
P10 cycles	2.50
P11 cycles	2.50
P12 cycles	7.00
P13 cycles	7.00
P14 cycles	5.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	14.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.33
Bytes prefetched	0.00
Bytes loaded	48.00
Bytes stored	112.00
Stride 0	10.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	7.69
Vectorization ratio load	20.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	51.92
Vector-efficiency ratio load	60.00
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	50.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	r4cum3p
Source file and lines	r4cum3p.F:115-131
Module	engine_linuxa64_ompi

The loop is defined in /home/hbollore/pop3/openradioss/OpenRadioss/engine/source/elements/spring/r4cum3p.F:115-131.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.50 to 4.00 cycles (1.88x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	7.50	7.50	2.50	2.50	7.00	7.00	5.00	0.00	0.00
cycles	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	7.50	7.50	2.50	2.50	7.00	7.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

INT

all	9%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 82cda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR D0, [X2], #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X22], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X14], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SSHLL V0.2D, V0.2S, #26	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D3, [X21], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FNEG D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNEG D6, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
SUBS X6, X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR D1, [X5], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D2, [X3], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D3, [X13], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MOV X15, V0.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X17, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP D0, D4, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR D5, [X12], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D6, [X18], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X16, X16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D1, [X8, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D2, [X9, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D3, [X11, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X0, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FNEG D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D5, [X9, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D6, [X11, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D4, [X0, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X8, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 82cda0 <r4cum3p_+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	r4cum3p
Source file and lines	r4cum3p.F:115-131
Module	engine_linuxa64_ompi

The loop is defined in /home/hbollore/pop3/openradioss/OpenRadioss/engine/source/elements/spring/r4cum3p.F:115-131.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 48 bytes. The binary loop is storing 112 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	7.50	7.50	2.50	2.50	7.00	7.00	5.00	0.00	0.00
cycles	0.50	0.50	2.08	2.08	2.00	2.00	1.92	1.92	7.50	7.50	2.50	2.50	7.00	7.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Data deps.	1.00
Overall L1	7.50

Vectorization ratios

INT

all	9%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	50%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	7%
load	20%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.93 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 82cda0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR D0, [X2], #12	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D1, [X22], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D2, [X14], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
SSHLL V0.2D, V0.2S, #26	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
LDR D3, [X21], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FNEG D5, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FNEG D6, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
SUBS X6, X6, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
STR D1, [X5], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D2, [X3], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D3, [X13], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
MOV X15, V0.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X17, D0	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP D0, D4, [X16, #1016]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR D5, [X12], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D6, [X18], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ADD X16, X16, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
STR D1, [X8, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D2, [X9, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D3, [X11, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X0, X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FNEG D0, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
STR D5, [X9, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D6, [X11, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D4, [X0, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X10], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
STR D0, [X8, X15]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
B.NE 82cda0 <r4cum3p_+0x360>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code