| Run orig_default | Run aocc_default | Run gcc_default | Run icx_2 | Run aocc_6 | Run gcc_7 |
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-31
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0775/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
|
| ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s |
| 4 | 39.36 | 39.24 | 98.33 | 100 | 45.63 | 3553.91 | 4 | 131.28 | 130.55 | 99.07 | 41.24 | 14.37 | 1206.1 | 3 | 39.12 | 38.99 | 98.08 | 100 | 45.73 | 3460.57 | 11 | 38.76 | 38.63 | 97.78 | 100 | 91.25 | 3609.04 | 4 | 38.54 | 38.55 | 98.49 | 100 | 29.17 | 3617.17 | 3 | 0.04 | 0.01 | 0.04 | 6.45 | 8.47 | 654.09 |
| | | | | 4 | 38.59 | 38.44 | 97.99 | 100 | 91.46 | 3509.25 |
| | | | | |
| Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 3) | Sum on 1 analyzed binary loop (exec - 11) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 2 analyzed binary loops (exec - 3, exec - 4) |
| Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count |
| Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | |
| Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 |
| Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 1 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 | Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA | 0 |
| Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | |
| Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | |
| More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 0 | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 0 | More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 0 |
| Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 |
| Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | |
| Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | |
| Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 |
| Use of masked instructions | 1 | Use of masked instructions | 0 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 |