| Run orig_default | Run icx_default | Run gcc_default | Run aocc_7 | Run icx_7 | Run gcc_1 |
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-31
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-35
| Loop Source Regions | - /beegfs/hackathon/users/eoseret/qaas_runs_test/179-312-0899/intel/HACCmkW/build/HACCmkW/src/Step10_orig.c: 19-31
|
| ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s | ASM Loop ID | Max Time Over Threads (s) | Time w.r.t. Wall Time (s) | Cov (%) | Vect. Ratio (%) | Vector Length Use (%) | GFLOP/s |
| 5 | 0.02 | 0.00 | 0.02 | 100 | 29.1 | 7410.43 | 4 | 17.01 | 16.87 | 92.66 | 100 | 91.25 | 10387.43 | 3 | 16.98 | 16.77 | 89.76 | 100 | 91.46 | 10069.12 | 5 | 0.03 | 0.00 | 0.02 | 100 | 29.1 | 7207.62 | 4 | 17.02 | 17.00 | 92.77 | 100 | 91.25 | 10285.56 | 3 | 16.89 | 16.70 | 89.77 | 100 | 91.46 | 10115.21 |
| | | | | |
| Sum on 1 analyzed binary loop (exec - 5) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 3) | Sum on 1 analyzed binary loop (exec - 5) | Sum on 1 analyzed binary loop (exec - 4) | Sum on 1 analyzed binary loop (exec - 3) |
| Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count | Analysis | Count |
| Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | | Loop Computation Issues | |
| Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 | Presence of expensive FP instructions | 1 |
| Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | | Control Flow Issues | |
| Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | | Data Access Issues | |
| More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | | More than 10% of the vector loads instructions are unaligned | 1 | More than 10% of the vector loads instructions are unaligned | 1 |
| Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 |
| Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | | Vectorization Roadblocks | |
| Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | 1 | Presence of 2 to 4 paths | | Presence of 2 to 4 paths | |
| Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | | Inefficient Vectorization | |
| Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 0 | Presence of special instructions executing on a single port | 1 | Presence of special instructions executing on a single port | 1 |
| Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 | Use of masked instructions | 1 |