OV - turborvb-serial.x - Loop 61545

	Loop Id: 61545	Module: turborvb-serial.x	Source: :0-0	Coverage: 0.41%

0x1ed31d0 VFMADD231PD	%ZMM0,%ZMM6,%ZMM8

0x1ed31d6 VFMADD231PD	%ZMM1,%ZMM6,%ZMM16

0x1ed31dc VFMADD231PD	%ZMM2,%ZMM6,%ZMM24

0x1ed31e2 VBROADCASTSD	-0x3f0(%RBP),%ZMM6    [1]

0x1ed31e9 VFMADD231PD	%ZMM0,%ZMM7,%ZMM9

0x1ed31ef PREFETCHT0	-0x200(%RBP)    [1]

0x1ed31f6 VFMADD231PD	%ZMM1,%ZMM7,%ZMM17

0x1ed31fc VFMADD231PD	%ZMM2,%ZMM7,%ZMM25

0x1ed3202 VBROADCASTSD	-0x3e8(%RBP),%ZMM7    [1]

0x1ed3209 VMOVUPD	-0x280(%RBX),%ZMM0    [3]

0x1ed3210 VMOVUPD	-0x240(%RBX),%ZMM1    [3]

0x1ed3217 VMOVUPD	-0x200(%RBX),%ZMM2    [3]

0x1ed321e VFMADD231PD	%ZMM3,%ZMM6,%ZMM8

0x1ed3224 VFMADD231PD	%ZMM4,%ZMM6,%ZMM16

0x1ed322a VFMADD231PD	%ZMM5,%ZMM6,%ZMM24

0x1ed3230 VBROADCASTSD	-0x3e0(%RBP),%ZMM6    [1]

0x1ed3237 VFMADD231PD	%ZMM3,%ZMM7,%ZMM9

0x1ed323d PREFETCHT0	-0x1c0(%RBP)    [1]

0x1ed3244 VFMADD231PD	%ZMM4,%ZMM7,%ZMM17

0x1ed324a VFMADD231PD	%ZMM5,%ZMM7,%ZMM25

0x1ed3250 VBROADCASTSD	-0x3d8(%RBP),%ZMM7    [1]

0x1ed3257 VMOVUPD	-0x1c0(%RBX),%ZMM3    [3]

0x1ed325e VMOVUPD	-0x180(%RBX),%ZMM4    [3]

0x1ed3265 VMOVUPD	-0x140(%RBX),%ZMM5    [3]

0x1ed326c VFMADD231PD	%ZMM0,%ZMM6,%ZMM8

0x1ed3272 VFMADD231PD	%ZMM1,%ZMM6,%ZMM16

0x1ed3278 VFMADD231PD	%ZMM2,%ZMM6,%ZMM24

0x1ed327e VBROADCASTSD	-0x3d0(%RBP),%ZMM6    [1]

0x1ed3285 VFMADD231PD	%ZMM0,%ZMM7,%ZMM9

0x1ed328b PREFETCHT0	-0x180(%RBP)    [1]

0x1ed3292 VFMADD231PD	%ZMM1,%ZMM7,%ZMM17

0x1ed3298 VFMADD231PD	%ZMM2,%ZMM7,%ZMM25

0x1ed329e VBROADCASTSD	-0x3c8(%RBP),%ZMM7    [1]

0x1ed32a5 VMOVUPD	-0x100(%RBX),%ZMM0    [3]

0x1ed32ac VMOVUPD	-0xc0(%RBX),%ZMM1    [3]

0x1ed32b3 VMOVUPD	-0x80(%RBX),%ZMM2    [3]

0x1ed32ba PREFETCHT2	-0x400(%RCX)    [2]

0x1ed32c1 VFMADD231PD	%ZMM3,%ZMM6,%ZMM8

0x1ed32c7 VFMADD231PD	%ZMM4,%ZMM6,%ZMM16

0x1ed32cd VFMADD231PD	%ZMM5,%ZMM6,%ZMM24

0x1ed32d3 VBROADCASTSD	-0x3c0(%RBP),%ZMM6    [1]

0x1ed32da VFMADD231PD	%ZMM3,%ZMM7,%ZMM9

0x1ed32e0 PREFETCHT0	-0x140(%RBP)    [1]

0x1ed32e7 VFMADD231PD	%ZMM4,%ZMM7,%ZMM17

0x1ed32ed VFMADD231PD	%ZMM5,%ZMM7,%ZMM25

0x1ed32f3 VBROADCASTSD	-0x3b8(%RBP),%ZMM7    [1]

0x1ed32fa LEA	0x40(%RCX),%RCX

0x1ed32fe VMOVUPD	-0x40(%RBX),%ZMM3    [3]

0x1ed3305 VMOVUPD	(%RBX),%ZMM4    [3]

0x1ed330b VMOVUPD	0x40(%RBX),%ZMM5    [3]

0x1ed3312 LEA	0x300(%RBX),%RBX

0x1ed3319 LEA	0x40(%RBP),%RBP

0x1ed331d SUB	$0x1,%RAX

0x1ed3321 JG	1ed31d0

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

Coverage (%)	Name	Source Location	Module

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks
Function	mkl_blas_avx512_zgemm_kernel_0
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	13.93
Front-end cycles	13.25
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	0.00
P4 cycles	12.00
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	16.15
Stall cycles (UFS)	2.52
Nb insns	54.00
Nb uops	53.00
Nb loads	25.00
Nb stores	0.00
Nb stack references	13.00
FLOP/cycle	24.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	192.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	52.00
Bytes prefetched	320.00
Bytes loaded	832.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	81.82
Vectorization ratio load	60.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	84.09
Vector-efficiency ratio load	65.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.15
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.21
Bottlenecks
Function	mkl_blas_avx512_zgemm_kernel_0
Source
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	16.00
CQA cycles if fully vectorized	13.93
Front-end cycles	13.25
DIV/SQRT cycles	12.00
P0 cycles	12.00
P1 cycles	12.50
P2 cycles	12.50
P3 cycles	0.00
P4 cycles	12.00
P5 cycles	1.00
P6 cycles	0.00
P7 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	16.15
Stall cycles (UFS)	2.52
Nb insns	54.00
Nb uops	53.00
Nb loads	25.00
Nb stores	0.00
Nb stack references	13.00
FLOP/cycle	24.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	192.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	52.00
Bytes prefetched	320.00
Bytes loaded	832.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	0.00
Stride unknown	2.00
Stride indirect	0.00
Vectorization ratio all	81.82
Vectorization ratio load	60.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	84.09
Vector-efficiency ratio load	65.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	mkl_blas_avx512_zgemm_kernel_0
Source file and lines
Module	turborvb-serial.x

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 84% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 13.93 cycles (1.15x speedup).

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please read your compiler manual
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 192 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 384 FP arithmetical operations:

192: addition or subtraction (all inside FMA instructions)
192: multiply (all inside FMA instructions)

The binary loop is prefetching 320 bytes (40 double precision FP elements). The binary loop is loading 832 bytes (104 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.46 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	53
loop length	344
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	14
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.00	3.00	12.50	12.50	0.00	12.00	1.00	0.00
cycles	12.00	12.00	12.50	12.50	0.00	12.00	1.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	16.15
Stall cycles	2.52
LB full (events)	5.47

Cycles summary

Front-end	13.25
Dispatch	12.50
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	81%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	84%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

40% of peak load performance is reached (52.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 1ed31d0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput
VFMADD231PD %ZMM0,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM1,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3f0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM0,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x200(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM1,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3e8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x280(%RBX),%ZMM0	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x240(%RBX),%ZMM1	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x200(%RBX),%ZMM2	1	0	0	0.50	0.50	0	0	5-6	0.50
VFMADD231PD %ZMM3,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM4,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3e0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM3,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x1c0(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM4,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3d8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x1c0(%RBX),%ZMM3	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x180(%RBX),%ZMM4	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x140(%RBX),%ZMM5	1	0	0	0.50	0.50	0	0	5-6	0.50
VFMADD231PD %ZMM0,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM1,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3d0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM0,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x180(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM1,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3c8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x100(%RBX),%ZMM0	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0xc0(%RBX),%ZMM1	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x80(%RBX),%ZMM2	1	0	0	0.50	0.50	0	0	5-6	0.50
PREFETCHT2 -0x400(%RCX)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM3,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM4,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3c0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM3,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x140(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM4,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3b8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
LEA 0x40(%RCX),%RCX	1	0	0.50	0	0	0.50	0	1	0.50
VMOVUPD -0x40(%RBX),%ZMM3	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD (%RBX),%ZMM4	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD 0x40(%RBX),%ZMM5	1	0	0	0.50	0.50	0	0	5-6	0.50
LEA 0x300(%RBX),%RBX	1	0	0.50	0	0	0.50	0	1	0.50
LEA 0x40(%RBP),%RBP	1	0	0.50	0	0	0.50	0	1	0.50
SUB $0x1,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25
JG 1ed31d0	1	0.50	0	0	0	0	0.50	0	0.50-1

Function	mkl_blas_avx512_zgemm_kernel_0
Source file and lines
Module	turborvb-serial.x

gain
potential
hint
expert

Vectorization

Details

81% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

60% of SSE/AVX loads are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Pass to your compiler a micro-architecture specialization option:
- Please read your compiler manual
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries
2. inform your compiler that your arrays are vector aligned: read your compiler manual.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 192 FMA (fused multiply-add) operations.

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vector unaligned load/store instructions

Detected 12 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 12 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries
inform your compiler that your arrays are vector aligned: read your compiler manual.

Type of elements and instruction set

24 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 384 FP arithmetical operations:

192: addition or subtraction (all inside FMA instructions)
192: multiply (all inside FMA instructions)

The binary loop is prefetching 320 bytes (40 double precision FP elements). The binary loop is loading 832 bytes (104 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.46 FP operations per loaded or stored byte.

General properties

nb instructions	54
nb uops	53
loop length	344
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	14
nb stack references	13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	13.25 cycles
front end	13.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7
uops	12.00	3.00	12.50	12.50	0.00	12.00	1.00	0.00
cycles	12.00	12.00	12.50	12.50	0.00	12.00	1.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Front-end and detailed OoO resources (UFS)

FE+BE cycles	16.15
Stall cycles	2.52
LB full (events)	5.47

Cycles summary

Front-end	13.25
Dispatch	12.50
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

all	81%
load	60%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	84%
load	65%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

40% of peak load performance is reached (52.00 out of 128.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 1ed31d0

Instruction	Nb FU	P0	P1	P2	P3	P5	P6	Latency	Recip. throughput
VFMADD231PD %ZMM0,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM1,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3f0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM0,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x200(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM1,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3e8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x280(%RBX),%ZMM0	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x240(%RBX),%ZMM1	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x200(%RBX),%ZMM2	1	0	0	0.50	0.50	0	0	5-6	0.50
VFMADD231PD %ZMM3,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM4,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3e0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM3,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x1c0(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM4,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3d8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x1c0(%RBX),%ZMM3	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x180(%RBX),%ZMM4	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x140(%RBX),%ZMM5	1	0	0	0.50	0.50	0	0	5-6	0.50
VFMADD231PD %ZMM0,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM1,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3d0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM0,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x180(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM1,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM2,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3c8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
VMOVUPD -0x100(%RBX),%ZMM0	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0xc0(%RBX),%ZMM1	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD -0x80(%RBX),%ZMM2	1	0	0	0.50	0.50	0	0	5-6	0.50
PREFETCHT2 -0x400(%RCX)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM3,%ZMM6,%ZMM8	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM4,%ZMM6,%ZMM16	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM6,%ZMM24	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3c0(%RBP),%ZMM6	1	0	0	0.50	0.50	0	0	5	0.50
VFMADD231PD %ZMM3,%ZMM7,%ZMM9	1	0.50	0	0	0	0.50	0	4	0.50
PREFETCHT0 -0x140(%RBP)	1	0	0	0.50	0.50	0	0	4-5	0.50
VFMADD231PD %ZMM4,%ZMM7,%ZMM17	1	0.50	0	0	0	0.50	0	4	0.50
VFMADD231PD %ZMM5,%ZMM7,%ZMM25	1	0.50	0	0	0	0.50	0	4	0.50
VBROADCASTSD -0x3b8(%RBP),%ZMM7	1	0	0	0.50	0.50	0	0	5	0.50
LEA 0x40(%RCX),%RCX	1	0	0.50	0	0	0.50	0	1	0.50
VMOVUPD -0x40(%RBX),%ZMM3	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD (%RBX),%ZMM4	1	0	0	0.50	0.50	0	0	5-6	0.50
VMOVUPD 0x40(%RBX),%ZMM5	1	0	0	0.50	0.50	0	0	5-6	0.50
LEA 0x300(%RBX),%RBX	1	0	0.50	0	0	0.50	0	1	0.50
LEA 0x40(%RBP),%RBP	1	0	0.50	0	0	0.50	0	1	0.50
SUB $0x1,%RAX	1	0.25	0.25	0	0	0.25	0.25	1	0.25
JG 1ed31d0	1	0.50	0	0	0	0	0.50	0	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Front-end and detailed OoO resources (UFS)

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code